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linux/drivers/clk/renesas
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Claudiu Beznea 0ab2d84f94 clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well 
If MSTOP is not added for both clocks in a coupled pair, and the clocks
are not disabled in the reverse order of their enable sequence, the MSTOP
may remain enabled when disabling the clocks.

This happens because rzg2l_mod_clock_endisable() executes for coupled
clocks only when a single clock from the pair is enabled. If one clock has
no MSTOP defined, it can result in the MSTOP configuration being left
active when the clocks are disabled out of order (i.e., not in the reverse
order of enabling).

Fixes: c496959527 ("clk: renesas: r9a08g045: Drop power domain instantiation")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250704134328.3614317-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-08 11:36:16 +02:00
..
clk-div6.c
clk-div6.h
clk-emev2.c clk: renesas: emev2: Remove obsolete clkdev registration 2023-07-27 14:32:41 +02:00
clk-mstp.c clk: Use of_property_present() 2024-08-02 16:53:38 -07:00
clk-r8a73a4.c clk: renesas: Remove duplicate and trailing empty lines 2024-10-01 09:13:38 +02:00
clk-r8a7740.c clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT 2024-04-25 10:38:19 +02:00
clk-r8a7778.c clk: renesas: Remove duplicate and trailing empty lines 2024-10-01 09:13:38 +02:00
clk-r8a7779.c clk: renesas: r8a7779: Remove struct r8a7779_cpg 2022-06-13 11:53:18 +02:00
clk-rz.c clk: renesas: rza1: Remove struct rz_cpg 2022-06-13 11:53:18 +02:00
clk-sh73a0.c clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT 2024-04-25 10:38:19 +02:00
clk-vbattb.c clk: renesas: vbattb: Add VBATTB clock driver 2024-11-06 08:52:45 +01:00
Kconfig clk: renesas: Add CPG/MSSR support to RZ/N2H SoC 2025-06-19 20:19:19 +02:00
Makefile clk: renesas: Add CPG/MSSR support to RZ/N2H SoC 2025-06-19 20:19:19 +02:00
r7s9210-cpg-mssr.c clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register 2025-06-10 10:20:45 +02:00
r8a774a1-cpg-mssr.c clk: renesas: rcar-gen3: Add ADG clocks 2023-08-15 11:34:43 +02:00
r8a774b1-cpg-mssr.c clk: renesas: rcar-gen3: Add ADG clocks 2023-08-15 11:34:43 +02:00
r8a774c0-cpg-mssr.c clk: renesas: rcar-gen3: Add ADG clocks 2023-08-15 11:34:43 +02:00
r8a774e1-cpg-mssr.c clk: renesas: rcar-gen3: Add ADG clocks 2023-08-15 11:34:43 +02:00
r8a779a0-cpg-mssr.c clk: renesas: r8a779a0: Add ISP core clocks 2025-02-03 11:07:05 +01:00
r8a779f0-cpg-mssr.c clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs 2024-07-30 10:44:19 +02:00
r8a779g0-cpg-mssr.c clk: renesas: r8a779g0: Add ISP core clocks 2025-02-03 11:07:05 +01:00
r8a779h0-cpg-mssr.c clk: renesas: r8a779h0: Add VSPX clock 2025-02-03 11:07:06 +01:00
r8a7742-cpg-mssr.c
r8a7743-cpg-mssr.c
r8a7745-cpg-mssr.c
r8a7790-cpg-mssr.c
r8a7791-cpg-mssr.c
r8a7792-cpg-mssr.c
r8a7794-cpg-mssr.c
r8a7795-cpg-mssr.c clk: renesas: r8a7795: Constify r8a7795_*_clks 2023-09-26 09:38:00 +02:00
r8a7796-cpg-mssr.c clk: renesas: rcar-gen3: Add ADG clocks 2023-08-15 11:34:43 +02:00
r8a77470-cpg-mssr.c
r8a77965-cpg-mssr.c clk: renesas: rcar-gen3: Add ADG clocks 2023-08-15 11:34:43 +02:00
r8a77970-cpg-mssr.c clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register 2025-06-10 10:20:45 +02:00
r8a77980-cpg-mssr.c clk: renesas: r8a77980: Add I2C5 clock 2023-03-30 16:44:04 +02:00
r8a77990-cpg-mssr.c clk: renesas: rcar-gen3: Add ADG clocks 2023-08-15 11:34:43 +02:00
r8a77995-cpg-mssr.c clk: renesas: rcar-gen3: Add ADG clocks 2023-08-15 11:34:43 +02:00
r9a06g032-clocks.c clk: renesas: r9a06g032: Use BIT macro consistently 2024-12-10 12:00:30 +01:00
r9a07g043-cpg.c clk: renesas: rzg2l: Add support for MSTOP in clock enable/disable API 2025-06-10 10:24:17 +02:00
r9a07g044-cpg.c clk: renesas: rzg2l: Add support for MSTOP in clock enable/disable API 2025-06-10 10:24:17 +02:00
r9a08g045-cpg.c clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well 2025-07-08 11:36:16 +02:00
r9a09g011-cpg.c clk: renesas: rzg2l: Add support for MSTOP in clock enable/disable API 2025-06-10 10:24:17 +02:00
r9a09g047-cpg.c clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs 2025-07-08 11:36:16 +02:00
r9a09g056-cpg.c clk: renesas: r9a09g056: Add XSPI clock/reset 2025-07-02 20:53:35 +02:00
r9a09g057-cpg.c clk: renesas: r9a09g057: Add XSPI clock/reset 2025-07-02 20:53:35 +02:00
r9a09g077-cpg.c clk: renesas: r9a09g077: Add RIIC module clocks 2025-07-02 20:51:46 +02:00
rcar-cpg-lib.c clk: renesas: Remove duplicate and trailing empty lines 2024-10-01 09:13:38 +02:00
rcar-cpg-lib.h clk: renesas: rcar-gen3: Switch to new SD clock handling 2021-11-19 11:32:39 +01:00
rcar-gen2-cpg.c clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register 2025-06-10 10:20:45 +02:00
rcar-gen2-cpg.h clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register 2025-06-10 10:20:45 +02:00
rcar-gen3-cpg.c clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register 2025-06-10 10:20:45 +02:00
rcar-gen3-cpg.h clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register 2025-06-10 10:20:45 +02:00
rcar-gen4-cpg.c clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register 2025-06-10 10:20:45 +02:00
rcar-gen4-cpg.h clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register 2025-06-10 10:20:45 +02:00
rcar-usb2-clock-sel.c clk: Switch back to struct platform_driver::remove() 2024-09-21 14:12:05 -07:00
renesas-cpg-mssr.c clk: renesas: Add CPG/MSSR support to RZ/N2H SoC 2025-06-19 20:19:19 +02:00
renesas-cpg-mssr.h clk: renesas: Add support for R9A09G077 SoC 2025-06-10 10:24:17 +02:00
rzg2l-cpg.c clk: renesas: rzg2l: Rename mstp_clock to mod_clock 2025-06-10 10:32:39 +02:00
rzg2l-cpg.h clk: renesas: rzg2l: Drop MSTOP based power domain support 2025-06-10 10:24:17 +02:00
rzv2h-cpg.c clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting 2025-07-02 20:53:35 +02:00
rzv2h-cpg.h clk: renesas: r9a09g056: Add XSPI clock/reset 2025-07-02 20:53:35 +02:00