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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
5cd33db569
The RZ/{G2L,V2L,G3S} CPG versions support a feature called MSTOP. Each
module has one or more MSTOP bits associated with it, and these bits
need to be configured along with the module clocks. Setting the MSTOP
bits switches the module between normal and standby states.
Previously, MSTOP support was abstracted through power domains (struct
generic_pm_domain::{power_on, power_off} APIs). With this abstraction,
the order of setting the MSTOP and CLKON bits was as follows:
Previous Order:
A/ Switching to Normal State (e.g., during probe):
1/ Clear module MSTOP bit
2/ Set module CLKON bit
B/ Switching to Standby State (e.g., during remove):
1/ Clear CLKON bit
2/ Set MSTOP bit
However, in some cases (when the clock is disabled through devres), the
order may have been (due to the issue described in link section):
1/ Set MSTOP bit
2/ Clear CLKON bit
Recently, the hardware team has suggested that the correct order to set
the MSTOP and CLKON bits is:
Updated Order:
A/ Switching to Normal State (e.g., during probe):
1/ Set CLKON bit
2/ Clear MSTOP bit
B/ Switching to Standby State (e.g., during remove):
1/ Set MSTOP bit
2/ Clear CLKON bit
To prevent future issues due to incorrect ordering, the MSTOP setup has
now been implemented in rzg2l_mod_clock_endisable(), ensuring compliance
with the sequence suggested in Figure 41.5: Module Standby Mode
Procedure from the RZ/G3S HW manual, Rev1.10.
Additionally, since multiple clocks of a single module may be mapped to
a single MSTOP bit, MSTOP setup is reference-counted.
Furthermore, as all modules start in the normal state after reset, if
the module clocks are disabled, the module state is switched to standby.
This prevents keeping the module in an invalid state, as recommended by
the hardware team.
Link: https://lore.kernel.org/all/20250215130849.227812-1-claudiu.beznea.uj@bp.renesas.com/
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250527112403.1254122-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
268 lines
9.9 KiB
C
268 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/V2M Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*
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* Based on r9a07g044-cpg.c
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/r9a09g011-cpg.h>
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#include "rzg2l-cpg.h"
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#define RZV2M_SAMPLL4_CLK1 0x104
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#define RZV2M_SAMPLL4_CLK2 0x108
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#define PLL4_CONF (RZV2M_SAMPLL4_CLK1 << 22 | RZV2M_SAMPLL4_CLK2 << 12)
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#define DIV_A DDIV_PACK(0x200, 0, 3)
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#define DIV_B DDIV_PACK(0x204, 0, 2)
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#define DIV_D DDIV_PACK(0x204, 4, 2)
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#define DIV_E DDIV_PACK(0x204, 8, 1)
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#define DIV_W DDIV_PACK(0x328, 0, 3)
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#define SEL_B SEL_PLL_PACK(0x214, 0, 1)
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#define SEL_CSI0 SEL_PLL_PACK(0x330, 0, 1)
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#define SEL_CSI4 SEL_PLL_PACK(0x330, 4, 1)
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#define SEL_D SEL_PLL_PACK(0x214, 1, 1)
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#define SEL_E SEL_PLL_PACK(0x214, 2, 1)
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#define SEL_SDI SEL_PLL_PACK(0x300, 0, 1)
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#define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1)
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = 0,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_MAIN_24,
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CLK_MAIN_2,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL2_800,
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CLK_PLL2_400,
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CLK_PLL2_200,
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CLK_PLL2_100,
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CLK_PLL4,
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CLK_DIV_A,
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CLK_DIV_B,
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CLK_DIV_D,
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CLK_DIV_E,
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CLK_DIV_W,
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CLK_SEL_B,
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CLK_SEL_B_D2,
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CLK_SEL_CSI0,
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CLK_SEL_CSI4,
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CLK_SEL_D,
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CLK_SEL_E,
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CLK_SEL_SDI,
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CLK_SEL_W0,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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/* Divider tables */
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static const struct clk_div_table dtable_diva[] = {
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{0, 1},
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{1, 2},
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{2, 3},
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{3, 4},
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{4, 6},
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{5, 12},
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{6, 24},
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{0, 0},
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};
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static const struct clk_div_table dtable_divb[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{3, 8},
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{0, 0},
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};
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static const struct clk_div_table dtable_divd[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{0, 0},
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};
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static const struct clk_div_table dtable_divw[] = {
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{0, 6},
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{1, 7},
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{2, 8},
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{3, 9},
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{4, 10},
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{5, 11},
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{6, 12},
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{0, 0},
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};
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/* Mux clock tables */
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static const char * const sel_b[] = { ".main", ".divb" };
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static const char * const sel_csi[] = { ".main_24", ".main" };
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static const char * const sel_d[] = { ".main", ".divd" };
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static const char * const sel_e[] = { ".main", ".dive" };
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static const char * const sel_w[] = { ".main", ".divw" };
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static const char * const sel_sdi[] = { ".main", ".pll2_200" };
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static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_FIXED(".main", CLK_MAIN, CLK_EXTAL, 1, 1),
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DEF_FIXED(".main_24", CLK_MAIN_24, CLK_MAIN, 1, 2),
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DEF_FIXED(".main_2", CLK_MAIN_2, CLK_MAIN, 1, 24),
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DEF_FIXED(".pll1", CLK_PLL1, CLK_MAIN_2, 498, 1),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_MAIN_2, 800, 1),
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DEF_FIXED(".pll2_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
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DEF_FIXED(".pll2_400", CLK_PLL2_400, CLK_PLL2_800, 1, 2),
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DEF_FIXED(".pll2_200", CLK_PLL2_200, CLK_PLL2_800, 1, 4),
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DEF_FIXED(".pll2_100", CLK_PLL2_100, CLK_PLL2_800, 1, 8),
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DEF_SAMPLL(".pll4", CLK_PLL4, CLK_MAIN_2, PLL4_CONF),
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DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva),
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DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb),
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DEF_DIV_RO(".divd", CLK_DIV_D, CLK_PLL2_200, DIV_D, dtable_divd),
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DEF_DIV_RO(".dive", CLK_DIV_E, CLK_PLL2_100, DIV_E, NULL),
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DEF_DIV_RO(".divw", CLK_DIV_W, CLK_PLL4, DIV_W, dtable_divw),
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DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b),
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DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d),
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DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e),
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DEF_MUX(".selsdi", CLK_SEL_SDI, SEL_SDI, sel_sdi),
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DEF_MUX(".selcsi0", CLK_SEL_CSI0, SEL_CSI0, sel_csi),
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DEF_MUX(".selcsi4", CLK_SEL_CSI4, SEL_CSI4, sel_csi),
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DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w),
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DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2),
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};
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static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
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DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2, 0),
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DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5, 0),
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DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0, 0),
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DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1, 0),
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DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2, 0),
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DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3, 0),
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DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4, 0),
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DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5, 0),
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DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6, 0),
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DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7, 0),
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DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8, 0),
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DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9, 0),
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DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10, 0),
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DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11, 0),
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DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8, 0),
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DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8, 0),
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DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9, 0),
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DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4, 0),
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DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5, 0),
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DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6, 0),
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DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12, 0),
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DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12, 0),
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DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0, 0),
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DEF_MOD("tim_clk_8", R9A09G011_TIM8_CLK, CLK_MAIN_2, 0x424, 4, 0),
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DEF_MOD("tim_clk_9", R9A09G011_TIM9_CLK, CLK_MAIN_2, 0x424, 5, 0),
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DEF_MOD("tim_clk_10", R9A09G011_TIM10_CLK, CLK_MAIN_2, 0x424, 6, 0),
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DEF_MOD("tim_clk_11", R9A09G011_TIM11_CLK, CLK_MAIN_2, 0x424, 7, 0),
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DEF_MOD("tim_clk_12", R9A09G011_TIM12_CLK, CLK_MAIN_2, 0x424, 8, 0),
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DEF_MOD("tim_clk_13", R9A09G011_TIM13_CLK, CLK_MAIN_2, 0x424, 9, 0),
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DEF_MOD("tim_clk_14", R9A09G011_TIM14_CLK, CLK_MAIN_2, 0x424, 10, 0),
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DEF_MOD("tim_clk_15", R9A09G011_TIM15_CLK, CLK_MAIN_2, 0x424, 11, 0),
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DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12, 0),
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DEF_MOD("cperi_grpc", R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E, 0x428, 0, 0),
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DEF_MOD("tim_clk_16", R9A09G011_TIM16_CLK, CLK_MAIN_2, 0x428, 4, 0),
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DEF_MOD("tim_clk_17", R9A09G011_TIM17_CLK, CLK_MAIN_2, 0x428, 5, 0),
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DEF_MOD("tim_clk_18", R9A09G011_TIM18_CLK, CLK_MAIN_2, 0x428, 6, 0),
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DEF_MOD("tim_clk_19", R9A09G011_TIM19_CLK, CLK_MAIN_2, 0x428, 7, 0),
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DEF_MOD("tim_clk_20", R9A09G011_TIM20_CLK, CLK_MAIN_2, 0x428, 8, 0),
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DEF_MOD("tim_clk_21", R9A09G011_TIM21_CLK, CLK_MAIN_2, 0x428, 9, 0),
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DEF_MOD("tim_clk_22", R9A09G011_TIM22_CLK, CLK_MAIN_2, 0x428, 10, 0),
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DEF_MOD("tim_clk_23", R9A09G011_TIM23_CLK, CLK_MAIN_2, 0x428, 11, 0),
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DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12, 0),
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DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13, 0),
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DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0, 0),
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DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4, 0),
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DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5, 0),
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DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6, 0),
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DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7, 0),
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DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8, 0),
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DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9, 0),
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DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10, 0),
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DEF_MOD("cperi_grpg", R9A09G011_CPERI_GRPG_PCLK, CLK_SEL_E, 0x438, 0, 0),
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DEF_MOD("cperi_grph", R9A09G011_CPERI_GRPH_PCLK, CLK_SEL_E, 0x438, 1, 0),
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DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4, 0),
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DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5, 0),
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DEF_MOD("csi0_clk", R9A09G011_CSI0_CLK, CLK_SEL_CSI0, 0x438, 8, 0),
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DEF_MOD("csi4_clk", R9A09G011_CSI4_CLK, CLK_SEL_CSI4, 0x438, 12, 0),
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DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0, 0),
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};
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static const struct rzg2l_reset r9a09g011_resets[] = {
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DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2),
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DEF_RST_MON(R9A09G011_SDI0_IXRST, 0x608, 0, 6),
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DEF_RST_MON(R9A09G011_SDI1_IXRST, 0x608, 1, 7),
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DEF_RST_MON(R9A09G011_EMM_IXRST, 0x608, 2, 8),
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DEF_RST(R9A09G011_USB_PRESET_N, 0x608, 7),
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DEF_RST(R9A09G011_USB_DRD_RESET, 0x608, 8),
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DEF_RST(R9A09G011_USB_ARESETN_P, 0x608, 9),
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DEF_RST(R9A09G011_USB_ARESETN_H, 0x608, 10),
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DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11),
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DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13),
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DEF_RST(R9A09G011_TIM_GPB_PRESETN, 0x614, 1),
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DEF_RST(R9A09G011_TIM_GPC_PRESETN, 0x614, 2),
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DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN, 0x614, 5, 23),
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DEF_RST_MON(R9A09G011_CSI_GPG_PRESETN, 0x614, 6, 22),
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DEF_RST_MON(R9A09G011_CSI_GPH_PRESETN, 0x614, 7, 23),
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DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8),
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DEF_RST(R9A09G011_IIC_GPB_PRESETN, 0x614, 9),
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DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19),
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};
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static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {
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MOD_CLK_BASE + R9A09G011_CA53_CLK,
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MOD_CLK_BASE + R9A09G011_CPERI_GRPB_PCLK,
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MOD_CLK_BASE + R9A09G011_CPERI_GRPC_PCLK,
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MOD_CLK_BASE + R9A09G011_CPERI_GRPF_PCLK,
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MOD_CLK_BASE + R9A09G011_CPERI_GRPG_PCLK,
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MOD_CLK_BASE + R9A09G011_CPERI_GRPH_PCLK,
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MOD_CLK_BASE + R9A09G011_GIC_CLK,
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MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK,
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MOD_CLK_BASE + R9A09G011_URT_PCLK,
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};
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const struct rzg2l_cpg_info r9a09g011_cpg_info = {
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/* Core Clocks */
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.core_clks = r9a09g011_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a09g011_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Critical Module Clocks */
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.crit_mod_clks = r9a09g011_crit_mod_clks,
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.num_crit_mod_clks = ARRAY_SIZE(r9a09g011_crit_mod_clks),
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/* Module Clocks */
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.mod_clks = r9a09g011_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a09g011_mod_clks),
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.num_hw_mod_clks = R9A09G011_CA53_CLK + 1,
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/* Resets */
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.resets = r9a09g011_resets,
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.num_resets = ARRAY_SIZE(r9a09g011_resets),
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.has_clk_mon_regs = false,
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};
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