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e6e54229f3
Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1) IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux clocks needed by these two GBETH IPs. Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250702005706.1200059-2-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
356 lines
13 KiB
C
356 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G3E CPG driver
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
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#include "rzv2h-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I,
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/* External Input Clocks */
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CLK_AUDIO_EXTAL,
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CLK_RTXIN,
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CLK_QEXTAL,
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/* PLL Clocks */
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CLK_PLLCM33,
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CLK_PLLCLN,
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CLK_PLLDTY,
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CLK_PLLCA55,
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CLK_PLLVDO,
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CLK_PLLETH,
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/* Internal Core Clocks */
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CLK_PLLCM33_DIV3,
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CLK_PLLCM33_DIV4,
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CLK_PLLCM33_DIV5,
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CLK_PLLCM33_DIV16,
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CLK_PLLCM33_GEAR,
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CLK_SMUX2_XSPI_CLK0,
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CLK_SMUX2_XSPI_CLK1,
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CLK_PLLCM33_XSPI,
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CLK_PLLCLN_DIV2,
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CLK_PLLCLN_DIV8,
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CLK_PLLCLN_DIV16,
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CLK_PLLCLN_DIV20,
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CLK_PLLDTY_ACPU,
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CLK_PLLDTY_ACPU_DIV2,
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CLK_PLLDTY_ACPU_DIV4,
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CLK_PLLDTY_DIV8,
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CLK_PLLETH_DIV_250_FIX,
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CLK_PLLETH_DIV_125_FIX,
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CLK_CSDIV_PLLETH_GBE0,
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CLK_CSDIV_PLLETH_GBE1,
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CLK_SMUX2_GBE0_TXCLK,
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CLK_SMUX2_GBE0_RXCLK,
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CLK_SMUX2_GBE1_TXCLK,
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CLK_SMUX2_GBE1_RXCLK,
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CLK_PLLDTY_DIV16,
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CLK_PLLVDO_CRU0,
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CLK_PLLVDO_GPU,
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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static const struct clk_div_table dtable_1_8[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{3, 8},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_4[] = {
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{0, 2},
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{1, 4},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_16[] = {
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{0, 2},
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{1, 4},
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{2, 8},
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{3, 16},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_64[] = {
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{0, 2},
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{1, 4},
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{2, 8},
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{3, 16},
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{4, 64},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_100[] = {
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{0, 2},
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{1, 10},
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{2, 100},
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{0, 0},
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};
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/* Mux clock tables */
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static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
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static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
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static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
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static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
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static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
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static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
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static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
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DEF_INPUT("rtxin", CLK_RTXIN),
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DEF_INPUT("qextal", CLK_QEXTAL),
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/* PLL Clocks */
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DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
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DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
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DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
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/* Internal Core Clocks */
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DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
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DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
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DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
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DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
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DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
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DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
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DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
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DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
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dtable_2_16),
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DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
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DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
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DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
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DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
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DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
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DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
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DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
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DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
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DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
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DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
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DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, CLK_PLLETH_DIV_250_FIX,
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CSDIV0_DIVCTL0, dtable_2_100),
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DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, CLK_PLLETH_DIV_250_FIX,
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CSDIV0_DIVCTL1, dtable_2_100),
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DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
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DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
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DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
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DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
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DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
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DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
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DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
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/* Core Clocks */
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DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
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DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,
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CDDIV1_DIVCTL0, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55,
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CDDIV1_DIVCTL1, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55,
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CDDIV1_DIVCTL2, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55,
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CDDIV1_DIVCTL3, dtable_1_8),
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DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
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DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
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DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I,
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CLK_PLLETH_DIV_125_FIX, 1, 1),
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DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
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CLK_PLLETH_DIV_125_FIX, 1, 1),
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};
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static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
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DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
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BUS_MSTOP_NONE),
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DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
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BUS_MSTOP(3, BIT(5))),
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DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
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BUS_MSTOP(1, BIT(0))),
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DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
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BUS_MSTOP(1, BIT(0))),
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DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
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BUS_MSTOP(5, BIT(12))),
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DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
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BUS_MSTOP(5, BIT(12))),
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DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
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BUS_MSTOP(5, BIT(13))),
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DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
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BUS_MSTOP(5, BIT(13))),
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DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
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BUS_MSTOP(3, BIT(14))),
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DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
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BUS_MSTOP(10, BIT(15))),
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DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
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BUS_MSTOP(10, BIT(15))),
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DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
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BUS_MSTOP(10, BIT(15))),
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DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
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BUS_MSTOP(3, BIT(13))),
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DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
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BUS_MSTOP(1, BIT(1))),
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DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
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BUS_MSTOP(1, BIT(2))),
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DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
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BUS_MSTOP(1, BIT(3))),
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DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
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BUS_MSTOP(1, BIT(4))),
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DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
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BUS_MSTOP(1, BIT(5))),
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DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
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BUS_MSTOP(1, BIT(6))),
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DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
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BUS_MSTOP(1, BIT(7))),
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DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
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BUS_MSTOP(1, BIT(8))),
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DEF_MOD("canfd_0_pclk", CLK_PLLCLN_DIV16, 9, 12, 4, 28,
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BUS_MSTOP(10, BIT(14))),
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DEF_MOD("canfd_0_clk_ram", CLK_PLLCLN_DIV8, 9, 13, 4, 29,
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BUS_MSTOP(10, BIT(14))),
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DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30,
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BUS_MSTOP(10, BIT(14))),
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DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
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BUS_MSTOP(4, BIT(5))),
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DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
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BUS_MSTOP(4, BIT(5))),
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DEF_MOD_NO_PM("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
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BUS_MSTOP(4, BIT(5))),
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DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
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BUS_MSTOP(8, BIT(5)), 1),
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DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
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BUS_MSTOP(8, BIT(5)), 1),
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DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
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BUS_MSTOP(8, BIT(5)), 1),
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DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
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BUS_MSTOP(8, BIT(5)), 1),
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DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
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BUS_MSTOP(8, BIT(5))),
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DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
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BUS_MSTOP(8, BIT(5))),
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DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
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BUS_MSTOP(8, BIT(6)), 1),
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DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
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BUS_MSTOP(8, BIT(6)), 1),
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DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
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BUS_MSTOP(8, BIT(6)), 1),
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DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
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BUS_MSTOP(8, BIT(6)), 1),
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DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
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BUS_MSTOP(8, BIT(6))),
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DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
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BUS_MSTOP(8, BIT(6))),
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DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16,
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BUS_MSTOP(3, BIT(4))),
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DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
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BUS_MSTOP(3, BIT(4))),
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DEF_MOD("ge3d_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
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BUS_MSTOP(3, BIT(4))),
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DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
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BUS_MSTOP(2, BIT(15))),
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};
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static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
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DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
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DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
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DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
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DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
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DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
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DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
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DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
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DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
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DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
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DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
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DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
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DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
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DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
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DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
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DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
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DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
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DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
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DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
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DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
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DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */
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DEF_RST(10, 2, 4, 19), /* CANFD_0_RSTC_N */
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DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
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DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
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DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
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DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
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DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
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DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
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DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
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DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
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DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
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DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
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DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */
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DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */
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DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */
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DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
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|
};
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|
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const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
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/* Core Clocks */
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.core_clks = r9a09g047_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a09g047_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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|
|
|
/* Module Clocks */
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.mod_clks = r9a09g047_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks),
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.num_hw_mod_clks = 28 * 16,
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|
|
|
/* Resets */
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.resets = r9a09g047_resets,
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|
.num_resets = ARRAY_SIZE(r9a09g047_resets),
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|
|
|
.num_mstop_bits = 208,
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|
};
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