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3d37ca1482
In a subsequent patch, the registration callback will need more parameters from cpg_mssr_priv (like another base address with clock controllers with double register block, and also, notifiers and rmw_lock). Instead of adding more parameters, move the needed parameters to a public sub-struct. Instead moving clks to this structure, which would have implied to add an allocation (and cleanup) for it, keep the way the allocation is done and just have a copy of the pointer in the public structure. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Link: https://lore.kernel.org/20250515141828.43444-5-thierry.bultel.yh@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
85 lines
2.9 KiB
C
85 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* R-Car Gen4 Clock Pulse Generator
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*
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*/
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#ifndef __CLK_RENESAS_RCAR_GEN4_CPG_H__
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#define __CLK_RENESAS_RCAR_GEN4_CPG_H__
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enum rcar_gen4_clk_types {
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CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_GEN4_PLL1,
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CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
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CLK_TYPE_GEN4_PLL5,
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CLK_TYPE_GEN4_PLL_F8_25, /* Fixed fractional 8.25 PLL */
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CLK_TYPE_GEN4_PLL_V8_25, /* Variable fractional 8.25 PLL */
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CLK_TYPE_GEN4_PLL_F9_24, /* Fixed fractional 9.24 PLL */
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CLK_TYPE_GEN4_PLL_V9_24, /* Variable fractional 9.24 PLL */
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CLK_TYPE_GEN4_SDSRC,
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CLK_TYPE_GEN4_SDH,
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CLK_TYPE_GEN4_SD,
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CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */
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CLK_TYPE_GEN4_Z,
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CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */
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CLK_TYPE_GEN4_RPCSRC,
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CLK_TYPE_GEN4_RPC,
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CLK_TYPE_GEN4_RPCD2,
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/* SoC specific definitions start here */
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CLK_TYPE_GEN4_SOC_BASE,
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};
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#define DEF_GEN4_SDH(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
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#define DEF_GEN4_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
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#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
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(_parent0) << 16 | (_parent1), \
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.div = (_div0) << 16 | (_div1), .offset = _md)
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#define DEF_GEN4_OSC(_name, _id, _parent, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
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#define DEF_GEN4_PLL_F8_25(_name, _idx, _id, _parent) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_F8_25, _parent, .offset = _idx)
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#define DEF_GEN4_PLL_V8_25(_name, _idx, _id, _parent) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V8_25, _parent, .offset = _idx)
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#define DEF_GEN4_PLL_F9_24(_name, _idx, _id, _parent) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_F9_24, _parent, .offset = _idx)
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#define DEF_GEN4_PLL_V9_24(_name, _idx, _id, _parent) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V9_24, _parent, .offset = _idx)
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#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \
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DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
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struct rcar_gen4_cpg_pll_config {
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u8 extal_div;
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u8 pll1_mult;
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u8 pll1_div;
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u8 pll5_mult;
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u8 pll5_div;
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u8 osc_prediv;
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};
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#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */
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#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */
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#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */
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#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */
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#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */
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struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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struct cpg_mssr_pub *pub);
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int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
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unsigned int clk_extalr, u32 mode);
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#endif
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