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Another feature of the ADF4371/ADF4372 is that the supply current to the RF8P and RF8N output stage can shut down until the ADF4371 achieves lock as measured by the digital lock detect circuitry. The mute to lock detect bit (MUTE_LD) in REG25 enables this function. Signed-off-by: Stefan Popa <stefan.popa@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
63 lines
1.4 KiB
YAML
63 lines
1.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iio/frequency/adf4371.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices ADF4371/ADF4372 Wideband Synthesizers
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maintainers:
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- Popa Stefan <stefan.popa@analog.com>
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description: |
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Analog Devices ADF4371/ADF4372 SPI Wideband Synthesizers
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https://www.analog.com/media/en/technical-documentation/data-sheets/adf4371.pdf
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https://www.analog.com/media/en/technical-documentation/data-sheets/adf4372.pdf
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properties:
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compatible:
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enum:
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- adi,adf4371
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- adi,adf4372
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reg:
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maxItems: 1
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clocks:
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description:
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Definition of the external clock (see clock/clock-bindings.txt)
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maxItems: 1
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clock-names:
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description:
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Must be "clkin"
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maxItems: 1
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adi,mute-till-lock-en:
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type: boolean
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description:
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If this property is present, then the supply current to RF8P and RF8N
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output stage will shut down until the ADF4371/ADF4372 achieves lock as
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measured by the digital lock detect circuitry.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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examples:
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- |
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spi0 {
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#address-cells = <1>;
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#size-cells = <0>;
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frequency@0 {
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compatible = "adi,adf4371";
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reg = <0>;
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spi-max-frequency = <1000000>;
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clocks = <&adf4371_clkin>;
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clock-names = "clkin";
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};
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};
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...
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