Alex Deucher d766e6a393 drm/amdgpu: switch ih handling to two levels (v3) ... Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2017-03-29 23:53:37 -04:00
..
amdgpu.h	drm/amdgpu: add 64bit doorbell functions (v2)	2017-03-29 23:53:36 -04:00
amdgpu_acp.c
amdgpu_acp.h
amdgpu_acpi.c
amdgpu_afmt.c	gpu: drm: amd/radeon: Convert printk(KERN_<LEVEL> to pr_<level>	2017-03-29 23:53:24 -04:00
amdgpu_amdkfd.c
amdgpu_amdkfd.h
amdgpu_amdkfd_gfx_v7.c
amdgpu_amdkfd_gfx_v8.c
amdgpu_atombios.c
amdgpu_atombios.h
amdgpu_atpx_handler.c	gpu: drm: amd/radeon: Convert printk(KERN_<LEVEL> to pr_<level>	2017-03-29 23:53:24 -04:00
amdgpu_benchmark.c
amdgpu_bios.c
amdgpu_bo_list.c
amdgpu_cgs.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
amdgpu_connectors.c
amdgpu_connectors.h
amdgpu_cs.c	drm/amdgpu: IOCTL interface for PRT support v4	2017-03-29 23:52:56 -04:00
amdgpu_ctx.c
amdgpu_device.c	drm/amdgpu: add 64bit doorbell functions (v2)	2017-03-29 23:53:36 -04:00
amdgpu_display.c
amdgpu_dpm.c	drm: Use pr_cont where appropriate	2017-03-29 23:53:24 -04:00
amdgpu_dpm.h	drm/amdgpu: implement read_sensor() for pre-powerplay chips	2017-03-29 23:53:03 -04:00
amdgpu_drv.c	drm/amdgpu: Merge pre/postclose hooks	2017-03-29 23:53:33 -04:00
amdgpu_drv.h
amdgpu_encoders.c
amdgpu_fb.c	gpu: drm: amd/radeon: Convert printk(KERN_<LEVEL> to pr_<level>	2017-03-29 23:53:24 -04:00
amdgpu_fence.c
amdgpu_gart.c
amdgpu_gds.h
amdgpu_gem.c	drm/amdgpu: IOCTL interface for PRT support v4	2017-03-29 23:52:56 -04:00
amdgpu_gfx.c
amdgpu_gfx.h
amdgpu_gtt_mgr.c
amdgpu_i2c.c
amdgpu_i2c.h
amdgpu_ib.c	drm/amdgpu: disable HDP flushes on APUs	2017-03-29 23:53:25 -04:00
amdgpu_ih.c
amdgpu_ih.h	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
amdgpu_ioc32.c
amdgpu_irq.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
amdgpu_irq.h	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
amdgpu_job.c
amdgpu_kms.c	drm/amdgpu: Merge pre/postclose hooks	2017-03-29 23:53:33 -04:00
amdgpu_mn.c
amdgpu_mode.h
amdgpu_object.c	drm/amdgpu: simplify reservation handling during buffer creation	2017-03-29 23:53:08 -04:00
amdgpu_object.h
amdgpu_pll.c
amdgpu_pll.h
amdgpu_pm.c	drm/amd/amdgpu: Update read_sensor calls to have size parameter (v3)	2017-03-29 23:52:59 -04:00
amdgpu_pm.h
amdgpu_powerplay.c	drm/amdgpu:fix powerplay logic	2017-03-29 23:52:37 -04:00
amdgpu_powerplay.h
amdgpu_prime.c
amdgpu_ring.c	drm/amdgpu: add 64bit wb functions	2017-03-29 23:53:35 -04:00
amdgpu_ring.h	drm/amdgpu: change wptr to 64 bits (v2)	2017-03-29 23:53:35 -04:00
amdgpu_sa.c
amdgpu_sync.c
amdgpu_sync.h
amdgpu_test.c	drm/amdgpu: remove unused sync testing	2017-03-29 23:53:29 -04:00
amdgpu_trace.h	drm/amdgpu: trace fence details in amdgpu_sched_run_job	2017-03-29 23:53:32 -04:00
amdgpu_trace_points.c
amdgpu_ttm.c
amdgpu_ttm.h
amdgpu_ucode.c
amdgpu_ucode.h
amdgpu_uvd.c
amdgpu_uvd.h
amdgpu_vce.c
amdgpu_vce.h
amdgpu_virt.c	drm/amdgpu:add lock_reset for SRIOV	2017-03-29 23:52:46 -04:00
amdgpu_virt.h	drm/amdgpu:use work instead of delay-work	2017-03-29 23:53:11 -04:00
amdgpu_vm.c	drm/amdgpu: fix PRT teardown on VM fini v3	2017-03-29 23:53:02 -04:00
amdgpu_vm.h	drm/amdgpu: fix PRT teardown on VM fini v3	2017-03-29 23:53:02 -04:00
amdgpu_vram_mgr.c
atom.c	drm/amdgpu: print full bios version in dmesg.	2017-03-29 23:53:26 -04:00
atom.h	drm/amdgpu: print full bios version in dmesg.	2017-03-29 23:53:26 -04:00
atombios_crtc.c
atombios_crtc.h
atombios_dp.c
atombios_dp.h
atombios_encoders.c
atombios_encoders.h
atombios_i2c.c
atombios_i2c.h
ci_dpm.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
ci_dpm.h	drm/amd/amdgpu: add power profile support for CI	2017-03-29 23:52:52 -04:00
ci_smc.c
cik.c
cik.h
cik_dpm.h
cik_ih.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
cik_ih.h
cik_sdma.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
cik_sdma.h
cikd.h	drm/amd: Spelling s/SDMA_WRTIE_SUB_OPCODE_TILED/SDMA_WRITE_SUB_OPCODE_TILED/	2017-03-29 23:53:21 -04:00
clearstate_ci.h
clearstate_defs.h
clearstate_si.h
clearstate_vi.h
cz_ih.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
cz_ih.h
dce_v6_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
dce_v6_0.h
dce_v8_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
dce_v8_0.h
dce_v10_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
dce_v10_0.h
dce_v11_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
dce_v11_0.h
dce_virtual.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
dce_virtual.h
gfx_v6_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
gfx_v6_0.h
gfx_v7_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
gfx_v7_0.h
gfx_v8_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
gfx_v8_0.h
gmc_v6_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
gmc_v6_0.h
gmc_v7_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
gmc_v7_0.h
gmc_v8_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
gmc_v8_0.h
iceland_ih.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
iceland_ih.h
iceland_sdma_pkt_open.h
Kconfig
kv_dpm.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
kv_dpm.h
kv_smc.c
Makefile
mxgpu_vi.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
mxgpu_vi.h	drm/amdgpu/virt: increase mailbox timeout to 5000ms	2017-03-29 23:52:38 -04:00
ObjectID.h
ppsmc.h
r600_dpm.h
sdma_v2_4.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
sdma_v2_4.h
sdma_v3_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
sdma_v3_0.h
si.c
si.h
si_dma.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
si_dma.h
si_dpm.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
si_dpm.h
si_enums.h
si_ih.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
si_ih.h
si_smc.c
sid.h
sislands_smc.h
tonga_ih.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
tonga_ih.h
tonga_sdma_pkt_open.h
uvd_v4_2.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
uvd_v4_2.h
uvd_v5_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
uvd_v5_0.h
uvd_v6_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
uvd_v6_0.h
vce_v2_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
vce_v2_0.h
vce_v3_0.c	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
vce_v3_0.h
vi.c	drm/amdgpu:cg & pg shouldn't active on VF device	2017-03-29 23:52:40 -04:00
vi.h	drm/amdgpu/gfx8: move CE&DE meta data structure to vi_structs.h	2017-03-29 23:53:31 -04:00
vi_dpm.h
vid.h