Alex Deucher d766e6a393 drm/amdgpu: switch ih handling to two levels (v3) ... Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2017-03-29 23:53:37 -04:00
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drm	drm/amdgpu: switch ih handling to two levels (v3)	2017-03-29 23:53:37 -04:00
host1x
ipu-v3	gpu: ipu-v3: only set non-zero AXI ID for IC when PRG is absent	2017-03-16 10:14:49 +01:00
vga	Pointer for Markus's image conversion work.	2017-03-14 15:07:33 +01:00
Makefile