Wesley Chalmers a659f2fdf8 drm/amd/display: Add interface to get Calibrated Avg Level from FIFO ... [WHY] Hardware has handed down a new sequence requiring the value of this register be read from clk_mgr. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-06-15 17:25:41 -04:00
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dcn_1_0_offset.h
dcn_1_0_sh_mask.h
dcn_2_0_0_offset.h
dcn_2_0_0_sh_mask.h
dcn_2_1_0_offset.h
dcn_2_1_0_sh_mask.h
dcn_3_0_0_offset.h	drm/amd/amdgpu: Add missing BASE_IDX to dcn register	2021-03-05 15:11:32 -05:00
dcn_3_0_0_sh_mask.h
dcn_3_0_1_offset.h	drm/amdgpu: add vangogh asic header files (v2)	2020-10-05 15:14:02 -04:00
dcn_3_0_1_sh_mask.h	drm/amd/display: Add interface to get Calibrated Avg Level from FIFO	2021-06-15 17:25:41 -04:00
dcn_3_0_2_offset.h	drm/amdgpu: Add and use seperate reg headers for dcn302	2020-11-10 14:15:08 -05:00
dcn_3_0_2_sh_mask.h	drm/amdgpu: Add and use seperate reg headers for dcn302	2020-11-10 14:15:08 -05:00
dcn_3_0_3_offset.h	drm/amd/display: Edit license info for beige goby DC files	2021-05-19 22:42:04 -04:00
dcn_3_0_3_sh_mask.h	drm/amd/display: Edit license info for beige goby DC files	2021-05-19 22:42:04 -04:00
dcn_3_1_2_offset.h	drm/amdgpu: add yellow carp asic header files (v3)	2021-06-04 16:03:05 -04:00
dcn_3_1_2_sh_mask.h	drm/amd/display: Add interface to get Calibrated Avg Level from FIFO	2021-06-15 17:25:41 -04:00
dpcs_3_0_0_offset.h
dpcs_3_0_0_sh_mask.h
dpcs_3_0_3_offset.h	drm/amd/display: Edit license info for beige goby DC files	2021-05-19 22:42:04 -04:00
dpcs_3_0_3_sh_mask.h	drm/amd/display: Edit license info for beige goby DC files	2021-05-19 22:42:04 -04:00