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Add definitions for XSPI core clock and Gigabit Ethernet PTP reference core clocks in the R9A09G047 CPG DT bindings header file. The clk_spi is modelled as a fixed divider clock with parent clk_spix2 and factor two as both parent and child share same gating bit. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250424081400.135028-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
24 lines
799 B
C
24 lines
799 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
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#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* Core Clock list */
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#define R9A09G047_SYS_0_PCLK 0
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#define R9A09G047_CA55_0_CORECLK0 1
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#define R9A09G047_CA55_0_CORECLK1 2
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#define R9A09G047_CA55_0_CORECLK2 3
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#define R9A09G047_CA55_0_CORECLK3 4
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#define R9A09G047_CA55_0_PERIPHCLK 5
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#define R9A09G047_CM33_CLK0 6
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#define R9A09G047_CST_0_SWCLKTCK 7
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#define R9A09G047_IOTOP_0_SHCLK 8
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#define R9A09G047_SPI_CLK_SPI 9
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#define R9A09G047_GBETH_0_CLK_PTP_REF_I 10
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#define R9A09G047_GBETH_1_CLK_PTP_REF_I 11
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#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
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