linux/include/dt-bindings/clock/renesas,r9a09g047-cpg.h

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 *
 * Copyright (C) 2024 Renesas Electronics Corp.
 */
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* Core Clock list */
#define R9A09G047_SYS_0_PCLK			0
#define R9A09G047_CA55_0_CORECLK0		1
#define R9A09G047_CA55_0_CORECLK1		2
#define R9A09G047_CA55_0_CORECLK2		3
#define R9A09G047_CA55_0_CORECLK3		4
#define R9A09G047_CA55_0_PERIPHCLK		5
#define R9A09G047_CM33_CLK0			6
#define R9A09G047_CST_0_SWCLKTCK		7
#define R9A09G047_IOTOP_0_SHCLK			8
#define R9A09G047_SPI_CLK_SPI			9
#define R9A09G047_GBETH_0_CLK_PTP_REF_I		10
#define R9A09G047_GBETH_1_CLK_PTP_REF_I		11

#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
dt-bindings: clock: renesas: Document RZ/G3E SoC CPG Document the device tree bindings for the Renesas RZ/G3E SoC Clock Pulse Generator (CPG). Also define constants for the core clocks of the RZ/G3E SoC. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241203105005.103927-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2024-12-03 10:49:31 +00:00			`/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)`
			`*`
			`* Copyright (C) 2024 Renesas Electronics Corp.`
			`*/`
			`#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__`
			`#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__`

			`#include <dt-bindings/clock/renesas-cpg-mssr.h>`

			`/* Core Clock list */`
			`#define R9A09G047_SYS_0_PCLK 0`
			`#define R9A09G047_CA55_0_CORECLK0 1`
			`#define R9A09G047_CA55_0_CORECLK1 2`
			`#define R9A09G047_CA55_0_CORECLK2 3`
			`#define R9A09G047_CA55_0_CORECLK3 4`
			`#define R9A09G047_CA55_0_PERIPHCLK 5`
			`#define R9A09G047_CM33_CLK0 6`
			`#define R9A09G047_CST_0_SWCLKTCK 7`
			`#define R9A09G047_IOTOP_0_SHCLK 8`
dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks Add definitions for XSPI core clock and Gigabit Ethernet PTP reference core clocks in the R9A09G047 CPG DT bindings header file. The clk_spi is modelled as a fixed divider clock with parent clk_spix2 and factor two as both parent and child share same gating bit. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250424081400.135028-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2025-04-24 09:13:54 +01:00			`#define R9A09G047_SPI_CLK_SPI 9`
			`#define R9A09G047_GBETH_0_CLK_PTP_REF_I 10`
			`#define R9A09G047_GBETH_1_CLK_PTP_REF_I 11`
dt-bindings: clock: renesas: Document RZ/G3E SoC CPG Document the device tree bindings for the Renesas RZ/G3E SoC Clock Pulse Generator (CPG). Also define constants for the core clocks of the RZ/G3E SoC. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241203105005.103927-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2024-12-03 10:49:31 +00:00
			`#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */`