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314b903c30
The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and ethernet (50Mhz) clocks. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
16 lines
461 B
C
16 lines
461 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H
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#define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H
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/* CMN PLL core clock. */
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#define IPQ5018_CMN_PLL_CLK 0
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/* The output clocks from CMN PLL of IPQ5018. */
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#define IPQ5018_XO_24MHZ_CLK 1
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#define IPQ5018_SLEEP_32KHZ_CLK 2
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#define IPQ5018_ETH_50MHZ_CLK 3
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#endif
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