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c0f1cbf795
The CMN PLL controller provides clocks to networking hardware blocks and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, and produces output clocks at fixed rates. These output rates are predetermined, and are unrelated to the input clock rate. The primary purpose of CMN PLL is to supply clocks to the networking hardware such as PPE (packet process engine), PCS and the externally connected switch or PHY device. The CMN PLL block also outputs fixed rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep clock supplied to GCC. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
22 lines
585 B
C
22 lines
585 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
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#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
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/* CMN PLL core clock. */
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#define CMN_PLL_CLK 0
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/* The output clocks from CMN PLL of IPQ9574. */
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#define XO_24MHZ_CLK 1
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#define SLEEP_32KHZ_CLK 2
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#define PCS_31P25MHZ_CLK 3
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#define NSS_1200MHZ_CLK 4
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#define PPE_353MHZ_CLK 5
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#define ETH0_50MHZ_CLK 6
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#define ETH1_50MHZ_CLK 7
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#define ETH2_50MHZ_CLK 8
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#define ETH_25MHZ_CLK 9
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#endif
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