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360a7a6477
Add support for the resets on Canaan Kendryte K230 SoC. The driver support CPU0, CPU1, L2 cache flush, hardware auto clear and software clear resets. Tested-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Link: https://lore.kernel.org/r/20250613-k230-reset-v4-2-e5266d2be440@pigmoral.tech Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
371 lines
13 KiB
C
371 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2022-2024 Canaan Bright Sight Co., Ltd
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* Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
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*
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* The reset management module in the K230 SoC provides reset time control
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* registers. For RST_TYPE_CPU0, RST_TYPE_CPU1 and RST_TYPE_SW_DONE, the period
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* during which reset is applied or removed while the clock is stopped can be
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* set up to 15 * 0.25 = 3.75 µs. For RST_TYPE_HW_DONE, that period can be set
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* up to 255 * 0.25 = 63.75 µs. For RST_TYPE_FLUSH, the reset bit is
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* automatically cleared by hardware when flush completes.
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*
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* Although this driver does not configure the reset time registers, delays have
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* been added to the assert, deassert, and reset operations to cover the maximum
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* reset time. Some reset types include done bits whose toggle does not
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* unambiguously signal whether hardware reset removal or clock-stop period
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* expiration occurred first. Delays are therefore retained for types with done
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* bits to ensure safe timing.
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*
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* Reference: K230 Technical Reference Manual V0.3.1
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* https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
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*/
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#include <linux/cleanup.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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#include <dt-bindings/reset/canaan,k230-rst.h>
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/**
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* enum k230_rst_type - K230 reset types
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* @RST_TYPE_CPU0: Reset type for CPU0
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* Automatically clears, has write enable and done bit, active high
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* @RST_TYPE_CPU1: Reset type for CPU1
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* Manually clears, has write enable and done bit, active high
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* @RST_TYPE_FLUSH: Reset type for CPU L2 cache flush
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* Automatically clears, has write enable, no done bit, active high
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* @RST_TYPE_HW_DONE: Reset type for hardware auto clear
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* Automatically clears, no write enable, has done bit, active high
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* @RST_TYPE_SW_DONE: Reset type for software manual clear
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* Manually clears, no write enable and done bit,
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* active high if ID is RST_SPI2AXI, otherwise active low
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*/
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enum k230_rst_type {
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RST_TYPE_CPU0,
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RST_TYPE_CPU1,
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RST_TYPE_FLUSH,
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RST_TYPE_HW_DONE,
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RST_TYPE_SW_DONE,
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};
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struct k230_rst_map {
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u32 offset;
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enum k230_rst_type type;
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u32 done;
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u32 reset;
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};
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struct k230_rst {
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struct reset_controller_dev rcdev;
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void __iomem *base;
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/* protect register read-modify-write */
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spinlock_t lock;
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};
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static const struct k230_rst_map k230_resets[] = {
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[RST_CPU0] = { 0x4, RST_TYPE_CPU0, BIT(12), BIT(0) },
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[RST_CPU1] = { 0xc, RST_TYPE_CPU1, BIT(12), BIT(0) },
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[RST_CPU0_FLUSH] = { 0x4, RST_TYPE_FLUSH, 0, BIT(4) },
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[RST_CPU1_FLUSH] = { 0xc, RST_TYPE_FLUSH, 0, BIT(4) },
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[RST_AI] = { 0x14, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
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[RST_VPU] = { 0x1c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
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[RST_HISYS] = { 0x2c, RST_TYPE_HW_DONE, BIT(4), BIT(0) },
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[RST_HISYS_AHB] = { 0x2c, RST_TYPE_HW_DONE, BIT(5), BIT(1) },
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[RST_SDIO0] = { 0x34, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
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[RST_SDIO1] = { 0x34, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
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[RST_SDIO_AXI] = { 0x34, RST_TYPE_HW_DONE, BIT(30), BIT(2) },
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[RST_USB0] = { 0x3c, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
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[RST_USB1] = { 0x3c, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
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[RST_USB0_AHB] = { 0x3c, RST_TYPE_HW_DONE, BIT(30), BIT(0) },
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[RST_USB1_AHB] = { 0x3c, RST_TYPE_HW_DONE, BIT(31), BIT(1) },
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[RST_SPI0] = { 0x44, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
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[RST_SPI1] = { 0x44, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
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[RST_SPI2] = { 0x44, RST_TYPE_HW_DONE, BIT(30), BIT(2) },
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[RST_SEC] = { 0x4c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
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[RST_PDMA] = { 0x54, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
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[RST_SDMA] = { 0x54, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
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[RST_DECOMPRESS] = { 0x5c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
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[RST_SRAM] = { 0x64, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
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[RST_SHRM_AXIM] = { 0x64, RST_TYPE_HW_DONE, BIT(30), BIT(2) },
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[RST_SHRM_AXIS] = { 0x64, RST_TYPE_HW_DONE, BIT(31), BIT(3) },
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[RST_NONAI2D] = { 0x6c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
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[RST_MCTL] = { 0x74, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
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[RST_ISP] = { 0x80, RST_TYPE_HW_DONE, BIT(29), BIT(6) },
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[RST_ISP_DW] = { 0x80, RST_TYPE_HW_DONE, BIT(28), BIT(5) },
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[RST_DPU] = { 0x88, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
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[RST_DISP] = { 0x90, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
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[RST_GPU] = { 0x98, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
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[RST_AUDIO] = { 0xa4, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
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[RST_TIMER0] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(0) },
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[RST_TIMER1] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(1) },
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[RST_TIMER2] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(2) },
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[RST_TIMER3] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(3) },
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[RST_TIMER4] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(4) },
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[RST_TIMER5] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(5) },
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[RST_TIMER_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(6) },
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[RST_HDI] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(7) },
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[RST_WDT0] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(12) },
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[RST_WDT1] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(13) },
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[RST_WDT0_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(14) },
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[RST_WDT1_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(15) },
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[RST_TS_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(16) },
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[RST_MAILBOX] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(17) },
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[RST_STC] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(18) },
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[RST_PMU] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(19) },
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[RST_LOSYS_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(0) },
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[RST_UART0] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(1) },
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[RST_UART1] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(2) },
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[RST_UART2] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(3) },
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[RST_UART3] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(4) },
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[RST_UART4] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(5) },
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[RST_I2C0] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(6) },
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[RST_I2C1] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(7) },
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[RST_I2C2] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(8) },
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[RST_I2C3] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(9) },
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[RST_I2C4] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(10) },
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[RST_JAMLINK0_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(11) },
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[RST_JAMLINK1_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(12) },
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[RST_JAMLINK2_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(13) },
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[RST_JAMLINK3_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(14) },
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[RST_CODEC_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(17) },
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[RST_GPIO_DB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(18) },
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[RST_GPIO_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(19) },
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[RST_ADC] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(20) },
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[RST_ADC_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(21) },
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[RST_PWM_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(22) },
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[RST_SHRM_APB] = { 0x64, RST_TYPE_SW_DONE, 0, BIT(1) },
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[RST_CSI0] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(0) },
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[RST_CSI1] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(1) },
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[RST_CSI2] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(2) },
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[RST_CSI_DPHY] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(3) },
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[RST_ISP_AHB] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(4) },
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[RST_M0] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(7) },
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[RST_M1] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(8) },
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[RST_M2] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(9) },
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[RST_SPI2AXI] = { 0xa8, RST_TYPE_SW_DONE, 0, BIT(0) }
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};
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static inline struct k230_rst *to_k230_rst(struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct k230_rst, rcdev);
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}
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static void k230_rst_clear_done(struct k230_rst *rstc, unsigned long id,
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bool write_en)
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{
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const struct k230_rst_map *rmap = &k230_resets[id];
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u32 reg;
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guard(spinlock_irqsave)(&rstc->lock);
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reg = readl(rstc->base + rmap->offset);
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reg |= rmap->done; /* write 1 to clear */
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if (write_en)
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reg |= rmap->done << 16;
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writel(reg, rstc->base + rmap->offset);
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}
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static int k230_rst_wait_and_clear_done(struct k230_rst *rstc, unsigned long id,
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bool write_en)
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{
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const struct k230_rst_map *rmap = &k230_resets[id];
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u32 reg;
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int ret;
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ret = readl_poll_timeout(rstc->base + rmap->offset, reg,
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reg & rmap->done, 10, 1000);
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if (ret) {
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dev_err(rstc->rcdev.dev, "Wait for reset done timeout\n");
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return ret;
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}
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k230_rst_clear_done(rstc, id, write_en);
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return 0;
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}
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static void k230_rst_update(struct k230_rst *rstc, unsigned long id,
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bool assert, bool write_en, bool active_low)
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{
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const struct k230_rst_map *rmap = &k230_resets[id];
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u32 reg;
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guard(spinlock_irqsave)(&rstc->lock);
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reg = readl(rstc->base + rmap->offset);
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if (assert ^ active_low)
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reg |= rmap->reset;
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else
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reg &= ~rmap->reset;
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if (write_en)
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reg |= rmap->reset << 16;
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writel(reg, rstc->base + rmap->offset);
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}
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static int k230_rst_assert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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struct k230_rst *rstc = to_k230_rst(rcdev);
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switch (k230_resets[id].type) {
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case RST_TYPE_CPU1:
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k230_rst_update(rstc, id, true, true, false);
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break;
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case RST_TYPE_SW_DONE:
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k230_rst_update(rstc, id, true, false,
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id == RST_SPI2AXI ? false : true);
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break;
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case RST_TYPE_CPU0:
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case RST_TYPE_FLUSH:
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case RST_TYPE_HW_DONE:
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return -EOPNOTSUPP;
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}
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/*
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* The time period when reset is applied but the clock is stopped for
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* RST_TYPE_CPU1 and RST_TYPE_SW_DONE can be set up to 3.75us. Delay
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* 10us to ensure proper reset timing.
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*/
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udelay(10);
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return 0;
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}
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static int k230_rst_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct k230_rst *rstc = to_k230_rst(rcdev);
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int ret = 0;
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switch (k230_resets[id].type) {
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case RST_TYPE_CPU1:
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k230_rst_update(rstc, id, false, true, false);
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ret = k230_rst_wait_and_clear_done(rstc, id, true);
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break;
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case RST_TYPE_SW_DONE:
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k230_rst_update(rstc, id, false, false,
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id == RST_SPI2AXI ? false : true);
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break;
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case RST_TYPE_CPU0:
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case RST_TYPE_FLUSH:
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case RST_TYPE_HW_DONE:
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return -EOPNOTSUPP;
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}
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/*
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* The time period when reset is removed but the clock is stopped for
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* RST_TYPE_CPU1 and RST_TYPE_SW_DONE can be set up to 3.75us. Delay
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* 10us to ensure proper reset timing.
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*/
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udelay(10);
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return ret;
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}
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static int k230_rst_reset(struct reset_controller_dev *rcdev, unsigned long id)
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{
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struct k230_rst *rstc = to_k230_rst(rcdev);
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const struct k230_rst_map *rmap = &k230_resets[id];
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u32 reg;
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int ret = 0;
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switch (rmap->type) {
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case RST_TYPE_CPU0:
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k230_rst_clear_done(rstc, id, true);
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k230_rst_update(rstc, id, true, true, false);
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ret = k230_rst_wait_and_clear_done(rstc, id, true);
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/*
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* The time period when reset is applied and removed but the
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* clock is stopped for RST_TYPE_CPU0 can be set up to 7.5us.
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* Delay 10us to ensure proper reset timing.
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*/
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udelay(10);
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break;
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case RST_TYPE_FLUSH:
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k230_rst_update(rstc, id, true, true, false);
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/* Wait flush request bit auto cleared by hardware */
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ret = readl_poll_timeout(rstc->base + rmap->offset, reg,
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!(reg & rmap->reset), 10, 1000);
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if (ret)
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dev_err(rcdev->dev, "Wait for flush done timeout\n");
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break;
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case RST_TYPE_HW_DONE:
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k230_rst_clear_done(rstc, id, false);
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k230_rst_update(rstc, id, true, false, false);
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ret = k230_rst_wait_and_clear_done(rstc, id, false);
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/*
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* The time period when reset is applied and removed but the
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* clock is stopped for RST_TYPE_HW_DONE can be set up to
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* 127.5us. Delay 200us to ensure proper reset timing.
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*/
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fsleep(200);
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break;
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case RST_TYPE_CPU1:
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case RST_TYPE_SW_DONE:
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k230_rst_assert(rcdev, id);
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ret = k230_rst_deassert(rcdev, id);
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break;
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}
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return ret;
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}
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static const struct reset_control_ops k230_rst_ops = {
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.reset = k230_rst_reset,
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.assert = k230_rst_assert,
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.deassert = k230_rst_deassert,
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};
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static int k230_rst_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct k230_rst *rstc;
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rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
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if (!rstc)
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return -ENOMEM;
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rstc->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(rstc->base))
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return PTR_ERR(rstc->base);
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spin_lock_init(&rstc->lock);
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rstc->rcdev.dev = dev;
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rstc->rcdev.owner = THIS_MODULE;
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rstc->rcdev.ops = &k230_rst_ops;
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rstc->rcdev.nr_resets = ARRAY_SIZE(k230_resets);
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rstc->rcdev.of_node = dev->of_node;
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return devm_reset_controller_register(dev, &rstc->rcdev);
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}
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static const struct of_device_id k230_rst_match[] = {
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{ .compatible = "canaan,k230-rst", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, k230_rst_match);
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static struct platform_driver k230_rst_driver = {
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.probe = k230_rst_probe,
|
|
.driver = {
|
|
.name = "k230-rst",
|
|
.of_match_table = k230_rst_match,
|
|
}
|
|
};
|
|
module_platform_driver(k230_rst_driver);
|
|
|
|
MODULE_AUTHOR("Junhui Liu <junhui.liu@pigmoral.tech>");
|
|
MODULE_DESCRIPTION("Canaan K230 reset driver");
|
|
MODULE_LICENSE("GPL");
|