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c4364048ba
Add new register offsets and PHY values for SM8750. Some of the previous definitions can be leveraged from older PHY versions as offsets within registers have not changed. This also adds the required PHY sequence that is recommended after running hardware characterization. Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com> Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-4-d58de3b41d34@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
64 lines
2.7 KiB
C
64 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_COM_V8_H_
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#define QCOM_PHY_QMP_QSERDES_COM_V8_H_
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/* Only for QMP V8 PHY - QSERDES COM registers */
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#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1 0x000
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#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1 0x004
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#define QSERDES_V8_COM_SSC_STEP_SIZE3_MODE1 0x008
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#define QSERDES_V8_COM_CP_CTRL_MODE1 0x010
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#define QSERDES_V8_COM_PLL_RCTRL_MODE1 0x014
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#define QSERDES_V8_COM_PLL_CCTRL_MODE1 0x018
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#define QSERDES_V8_COM_CORECLK_DIV_MODE1 0x01c
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#define QSERDES_V8_COM_LOCK_CMP1_MODE1 0x020
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#define QSERDES_V8_COM_LOCK_CMP2_MODE1 0x024
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#define QSERDES_V8_COM_DEC_START_MODE1 0x028
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#define QSERDES_V8_COM_DEC_START_MSB_MODE1 0x02c
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#define QSERDES_V8_COM_DIV_FRAC_START1_MODE1 0x030
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#define QSERDES_V8_COM_DIV_FRAC_START2_MODE1 0x034
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#define QSERDES_V8_COM_DIV_FRAC_START3_MODE1 0x038
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#define QSERDES_V8_COM_HSCLK_SEL_1 0x03c
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#define QSERDES_V8_COM_VCO_TUNE1_MODE1 0x048
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#define QSERDES_V8_COM_VCO_TUNE2_MODE1 0x04c
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#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x050
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#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x054
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#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058
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#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c
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#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0 0x060
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#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0 0x064
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#define QSERDES_V8_COM_CP_CTRL_MODE0 0x070
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#define QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074
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#define QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078
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#define QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080
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#define QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084
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#define QSERDES_V8_COM_DEC_START_MODE0 0x088
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#define QSERDES_V8_COM_DEC_START_MSB_MODE0 0x08c
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#define QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090
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#define QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094
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#define QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098
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#define QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8
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#define QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac
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#define QSERDES_V8_COM_BG_TIMER 0x0bc
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#define QSERDES_V8_COM_SSC_EN_CENTER 0x0c0
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#define QSERDES_V8_COM_SSC_PER1 0x0cc
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#define QSERDES_V8_COM_SSC_PER2 0x0d0
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#define QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc
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#define QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8
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#define QSERDES_V8_COM_SYSCLK_EN_SEL 0x110
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#define QSERDES_V8_COM_RESETSM_CNTRL 0x118
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#define QSERDES_V8_COM_LOCK_CMP_CFG 0x124
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#define QSERDES_V8_COM_VCO_TUNE_MAP 0x140
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#define QSERDES_V8_COM_CORE_CLK_EN 0x170
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#define QSERDES_V8_COM_CMN_CONFIG_1 0x174
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#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4
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#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8
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#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac
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#define QSERDES_V8_COM_ADDITIONAL_MISC 0x1b4
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#define QSERDES_V8_COM_CMN_STATUS 0x2c8
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#define QSERDES_V8_COM_C_READY_STATUS 0x2f0
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#endif
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