mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
65 lines
2.7 KiB
C
65 lines
2.7 KiB
C
![]() |
/* SPDX-License-Identifier: GPL-2.0 */
|
||
|
/*
|
||
|
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
|
||
|
*/
|
||
|
|
||
|
#ifndef QCOM_PHY_QMP_QSERDES_COM_V8_H_
|
||
|
#define QCOM_PHY_QMP_QSERDES_COM_V8_H_
|
||
|
|
||
|
/* Only for QMP V8 PHY - QSERDES COM registers */
|
||
|
#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1 0x000
|
||
|
#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1 0x004
|
||
|
#define QSERDES_V8_COM_SSC_STEP_SIZE3_MODE1 0x008
|
||
|
#define QSERDES_V8_COM_CP_CTRL_MODE1 0x010
|
||
|
#define QSERDES_V8_COM_PLL_RCTRL_MODE1 0x014
|
||
|
#define QSERDES_V8_COM_PLL_CCTRL_MODE1 0x018
|
||
|
#define QSERDES_V8_COM_CORECLK_DIV_MODE1 0x01c
|
||
|
#define QSERDES_V8_COM_LOCK_CMP1_MODE1 0x020
|
||
|
#define QSERDES_V8_COM_LOCK_CMP2_MODE1 0x024
|
||
|
#define QSERDES_V8_COM_DEC_START_MODE1 0x028
|
||
|
#define QSERDES_V8_COM_DEC_START_MSB_MODE1 0x02c
|
||
|
#define QSERDES_V8_COM_DIV_FRAC_START1_MODE1 0x030
|
||
|
#define QSERDES_V8_COM_DIV_FRAC_START2_MODE1 0x034
|
||
|
#define QSERDES_V8_COM_DIV_FRAC_START3_MODE1 0x038
|
||
|
#define QSERDES_V8_COM_HSCLK_SEL_1 0x03c
|
||
|
#define QSERDES_V8_COM_VCO_TUNE1_MODE1 0x048
|
||
|
#define QSERDES_V8_COM_VCO_TUNE2_MODE1 0x04c
|
||
|
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x050
|
||
|
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x054
|
||
|
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058
|
||
|
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c
|
||
|
#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0 0x060
|
||
|
#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0 0x064
|
||
|
#define QSERDES_V8_COM_CP_CTRL_MODE0 0x070
|
||
|
#define QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074
|
||
|
#define QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078
|
||
|
#define QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080
|
||
|
#define QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084
|
||
|
#define QSERDES_V8_COM_DEC_START_MODE0 0x088
|
||
|
#define QSERDES_V8_COM_DEC_START_MSB_MODE0 0x08c
|
||
|
#define QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090
|
||
|
#define QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094
|
||
|
#define QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098
|
||
|
#define QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8
|
||
|
#define QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac
|
||
|
#define QSERDES_V8_COM_BG_TIMER 0x0bc
|
||
|
#define QSERDES_V8_COM_SSC_EN_CENTER 0x0c0
|
||
|
#define QSERDES_V8_COM_SSC_PER1 0x0cc
|
||
|
#define QSERDES_V8_COM_SSC_PER2 0x0d0
|
||
|
#define QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc
|
||
|
#define QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8
|
||
|
#define QSERDES_V8_COM_SYSCLK_EN_SEL 0x110
|
||
|
#define QSERDES_V8_COM_RESETSM_CNTRL 0x118
|
||
|
#define QSERDES_V8_COM_LOCK_CMP_CFG 0x124
|
||
|
#define QSERDES_V8_COM_VCO_TUNE_MAP 0x140
|
||
|
#define QSERDES_V8_COM_CORE_CLK_EN 0x170
|
||
|
#define QSERDES_V8_COM_CMN_CONFIG_1 0x174
|
||
|
#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4
|
||
|
#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8
|
||
|
#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac
|
||
|
#define QSERDES_V8_COM_ADDITIONAL_MISC 0x1b4
|
||
|
#define QSERDES_V8_COM_CMN_STATUS 0x2c8
|
||
|
#define QSERDES_V8_COM_C_READY_STATUS 0x2f0
|
||
|
|
||
|
#endif
|