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03aa45d6c6
Update the PHY settings to align with the latest PCIe PHY Hardware Programming Guide for both PCIe controllers on the SA8775P platform. Add the ln_shrd region for SA8775P, incorporating new register writes as specified in the updated Hardware Programming Guide. Update pcs table for QCS8300, since both QCS8300 and SA8775P are closely related and share same pcs settings. Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250617-update_phy-v5-1-2df83ed6a373@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
21 lines
669 B
C
21 lines
669 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022, Linaro Ltd.
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*/
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#ifndef QCOM_PHY_QMP_PCS_V5_20_H_
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#define QCOM_PHY_QMP_PCS_V5_20_H_
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#define QPHY_V5_20_PCS_INSIG_SW_CTRL7 0x060
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#define QPHY_V5_20_PCS_INSIG_MX_CTRL7 0x07c
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#define QPHY_V5_20_PCS_LOCK_DETECT_CONFIG1 0x0c4
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#define QPHY_V5_20_PCS_LOCK_DETECT_CONFIG2 0x0c8
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#define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170
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#define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188
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#define QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG1 0x1b8
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#define QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG2 0x1bc
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#define QPHY_V5_20_PCS_EQ_CONFIG2 0x1d8
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#define QPHY_V5_20_PCS_EQ_CONFIG4 0x1e0
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#define QPHY_V5_20_PCS_EQ_CONFIG5 0x1e4
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#endif
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