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linux/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h

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phy: qcom-qmp-pcie: Fix sm8450_qmp_gen4x2_pcie_pcs_tbl[] register names sm8450_qmp_gen4x2_pcie_pcs_tbl[] contains the init sequence for PCS registers of QMP PHY v5.20. So use the v5.20 specific register names. Only major change is the rename of PCS_EQ_CONFIG{2/3} registers to PCS_EQ_CONFIG{4/5}. Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20221102081835.41892-2-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-02 13:48:35 +05:30
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2022, Linaro Ltd.
*/
#ifndef QCOM_PHY_QMP_PCS_V5_20_H_
#define QCOM_PHY_QMP_PCS_V5_20_H_
phy: qcom-qmp-pcie: add endpoint support for sa8775p Add support for dual lane end point mode PHY found on sa8755p platform. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1697715430-30820-4-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-19 17:07:08 +05:30
#define QPHY_V5_20_PCS_INSIG_SW_CTRL7 0x060
#define QPHY_V5_20_PCS_INSIG_MX_CTRL7 0x07c
phy: qcom: qmp-pcie: Update PHY settings for QCS8300 & SA8775P Update the PHY settings to align with the latest PCIe PHY Hardware Programming Guide for both PCIe controllers on the SA8775P platform. Add the ln_shrd region for SA8775P, incorporating new register writes as specified in the updated Hardware Programming Guide. Update pcs table for QCS8300, since both QCS8300 and SA8775P are closely related and share same pcs settings. Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250617-update_phy-v5-1-2df83ed6a373@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-17 17:08:19 +05:30
#define QPHY_V5_20_PCS_LOCK_DETECT_CONFIG1 0x0c4
#define QPHY_V5_20_PCS_LOCK_DETECT_CONFIG2 0x0c8
phy: qcom-qmp-pcie: Fix sm8450_qmp_gen4x2_pcie_pcs_tbl[] register names sm8450_qmp_gen4x2_pcie_pcs_tbl[] contains the init sequence for PCS registers of QMP PHY v5.20. So use the v5.20 specific register names. Only major change is the rename of PCS_EQ_CONFIG{2/3} registers to PCS_EQ_CONFIG{4/5}. Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20221102081835.41892-2-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-02 13:48:35 +05:30
#define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170
#define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188
phy: qcom: qmp-pcie: Update PHY settings for QCS8300 & SA8775P Update the PHY settings to align with the latest PCIe PHY Hardware Programming Guide for both PCIe controllers on the SA8775P platform. Add the ln_shrd region for SA8775P, incorporating new register writes as specified in the updated Hardware Programming Guide. Update pcs table for QCS8300, since both QCS8300 and SA8775P are closely related and share same pcs settings. Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250617-update_phy-v5-1-2df83ed6a373@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-17 17:08:19 +05:30
#define QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG1 0x1b8
#define QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG2 0x1bc
phy: qcom-qmp: Add support for SDX65 QMP PCIe PHY The PCIe PHY version used in SDX65 is v5.20 which has different register offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are used for init sequence and PHY status. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-17 12:08:34 +05:30
#define QPHY_V5_20_PCS_EQ_CONFIG2 0x1d8
phy: qcom-qmp-pcie: Fix sm8450_qmp_gen4x2_pcie_pcs_tbl[] register names sm8450_qmp_gen4x2_pcie_pcs_tbl[] contains the init sequence for PCS registers of QMP PHY v5.20. So use the v5.20 specific register names. Only major change is the rename of PCS_EQ_CONFIG{2/3} registers to PCS_EQ_CONFIG{4/5}. Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20221102081835.41892-2-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-11-02 13:48:35 +05:30
#define QPHY_V5_20_PCS_EQ_CONFIG4 0x1e0
#define QPHY_V5_20_PCS_EQ_CONFIG5 0x1e4
#endif
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