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f9d35dd39b
The PCS_LANE1 region isn't a part of the PCS_PCIE region. It was handled this way as it simplified handled of devices with the old bindings. Nowadays it can be handled as is, without hacks. Split the PCS_LANE1 region from the PCS_PCIE / PCS_MISC region space. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-4-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
20 lines
660 B
C
20 lines
660 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
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#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
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#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
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#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
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#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
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#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
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#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
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#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
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#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x024
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#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x028
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#endif
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