linux/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
 */

#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_

#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE	0x01c
#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS		0x090
#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1			0x0a0
#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME		0x0f0
#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME		0x0f4
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2		0x0fc
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5		0x108

#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2		0x024
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2		0x028

#endif
phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers Split registers definitions belonging allegedly to 4.20 and 5.20 QMP PHYs. They are used for the PCIe QMP PHYs, which have no good open source reference. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-20-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 2022-07-05 12:43:11 +03:00			`/* SPDX-License-Identifier: GPL-2.0 */`
			`/*`
			`* Copyright (c) 2017, The Linux Foundation. All rights reserved.`
			`*/`

			`#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_`
			`#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_`

phy: qcom-qmp-pcie: Add RC init sequence for SDX55 Add PCIe RC init sequence making use of the common init sequence. The RC mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and powerdown. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230308082424.140224-13-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 2023-03-08 13:54:23 +05:30			`#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c`
			`#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090`
phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers Split registers definitions belonging allegedly to 4.20 and 5.20 QMP PHYs. They are used for the PCIe QMP PHYs, which have no good open source reference. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-20-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 2022-07-05 12:43:11 +03:00			`#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0`
			`#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0`
			`#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4`
			`#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc`
			`#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108`
phy: qualcomm: qmp-pcie: split PCS_LANE1 region The PCS_LANE1 region isn't a part of the PCS_PCIE region. It was handled this way as it simplified handled of devices with the old bindings. Nowadays it can be handled as is, without hacks. Split the PCS_LANE1 region from the PCS_PCIE / PCS_MISC region space. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-4-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 2024-10-21 13:33:10 +03:00
			`#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x024`
			`#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x028`
phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers Split registers definitions belonging allegedly to 4.20 and 5.20 QMP PHYs. They are used for the PCIe QMP PHYs, which have no good open source reference. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-20-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 2022-07-05 12:43:11 +03:00
			`#endif`