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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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03aa45d6c6
Update the PHY settings to align with the latest PCIe PHY Hardware Programming Guide for both PCIe controllers on the SA8775P platform. Add the ln_shrd region for SA8775P, incorporating new register writes as specified in the updated Hardware Programming Guide. Update pcs table for QCS8300, since both QCS8300 and SA8775P are closely related and share same pcs settings. Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250617-update_phy-v5-1-2df83ed6a373@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
5134 lines
214 KiB
C
5134 lines
214 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/phy/pcie.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <dt-bindings/phy/phy-qcom-qmp.h>
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#include "phy-qcom-qmp-common.h"
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#include "phy-qcom-qmp.h"
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#include "phy-qcom-qmp-pcs-misc-v3.h"
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#include "phy-qcom-qmp-pcs-pcie-v4.h"
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#include "phy-qcom-qmp-pcs-pcie-v4_20.h"
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#include "phy-qcom-qmp-pcs-pcie-v5.h"
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#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
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#include "phy-qcom-qmp-pcs-pcie-v6.h"
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#include "phy-qcom-qmp-pcs-pcie-v6_20.h"
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#include "phy-qcom-qmp-pcs-pcie-v6_30.h"
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#include "phy-qcom-qmp-pcs-v6_30.h"
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#include "phy-qcom-qmp-pcie-qhp.h"
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#define PHY_INIT_COMPLETE_TIMEOUT 10000
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/* set of registers with offsets different per-PHY */
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enum qphy_reg_layout {
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/* PCS registers */
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QPHY_SW_RESET,
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QPHY_START_CTRL,
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QPHY_PCS_STATUS,
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QPHY_PCS_POWER_DOWN_CONTROL,
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/* Keep last to ensure regs_layout arrays are properly initialized */
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QPHY_LAYOUT_SIZE
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};
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static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
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[QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
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[QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
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};
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static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
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[QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
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[QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
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};
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static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_SW_RESET] = 0x00,
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[QPHY_START_CTRL] = 0x08,
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[QPHY_PCS_STATUS] = 0x2ac,
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[QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
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};
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static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
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[QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
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[QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
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};
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static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
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[QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
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[QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
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};
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static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET,
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[QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL,
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[QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1,
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[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
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};
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static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
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};
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static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
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};
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static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
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};
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static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
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};
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static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
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QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
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QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
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QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
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QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
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};
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static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
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};
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static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
|
|
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
|
|
QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
|
|
QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
|
|
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x73),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x80),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x14),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x10),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x06),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl qcs615_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x9),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x4),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xd),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x35),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x4),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x30),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl qcs615_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
|
|
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl qcs615_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
|
|
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
|
|
QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
|
|
QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl qcs615_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_SIGDET_CNTRL, 0x7),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
|
|
QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl qcs8300_qmp_gen4x2_pcie_rx_alt_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
|
|
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
|
|
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
|
|
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
|
|
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
|
|
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
|
|
QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
|
|
QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
|
|
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45),
|
|
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a, 1),
|
|
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b, 2),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
|
|
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, 1),
|
|
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38, 2),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x18),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0x7a),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_txz_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rxz_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0x23),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x38),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xe4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x69),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, BIT(0)),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_G3S2_PRE_GAIN, 0x2e),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_RX_SIGDET_LVL, 0x99),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG4, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG5, 0x22),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG, 0x04),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG2, 0x02),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_EQ_CONFIG1, 0x16),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5, 0x02),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN, 0x2e),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1, 0x03),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3, 0x28),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5, 0x18),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5, 0x7a),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5, 0x8a),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME, 0x27),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME, 0x27),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG, 0xc0),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2, 0x1d),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
|
QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_lane1_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_lane1_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
|
|
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
|
|
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
|
|
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
|
|
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
|
|
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xe4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xe4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xb3),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xed),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xe5),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x8d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xd6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x0f),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V5_20_PCS_G3_RXEQEVAL_TIME, 0x27),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V5_20_PCS_G4_RXEQEVAL_TIME, 0x27),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_alt_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LOCK_DETECT_CONFIG1, 0xff),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LOCK_DETECT_CONFIG2, 0x89),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG1, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG2, 0x50),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_v5_LN_SHRD_UCDR_PI_CTRL2, 0x00),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xb3),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xe4),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xe6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xd6),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x06),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
|
|
};
|
|
|
|
|
|
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_MX_CTRL7, 0x00),
|
|
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_SW_CTRL2, 0x01),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_MX_CTRL2, 0x01),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_tx_tbl[] = {
|
|
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_BIST_MODE_LANENO, 0x00, 2),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
|
|
QMP_PHY_INIT_CFG(QPHY_V6_PCS_G3S2_PRE_GAIN, 0x2e),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x06),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x28),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x0d),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x00),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0xff),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x09),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x19),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE1, 0x03),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
|
|
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
|
|
};
|
|
|
|
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl[] = {
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x14),
|
|
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
|
|
};
|
|
|
|
struct qmp_pcie_offsets {
|
|
u16 serdes;
|
|
u16 pcs;
|
|
u16 pcs_misc;
|
|
u16 pcs_lane1;
|
|
u16 tx;
|
|
u16 rx;
|
|
u16 tx2;
|
|
u16 rx2;
|
|
u16 txz;
|
|
u16 rxz;
|
|
u16 ln_shrd;
|
|
};
|
|
|
|
struct qmp_phy_cfg_tbls {
|
|
const struct qmp_phy_init_tbl *serdes;
|
|
int serdes_num;
|
|
const struct qmp_phy_init_tbl *tx;
|
|
int tx_num;
|
|
const struct qmp_phy_init_tbl *rx;
|
|
int rx_num;
|
|
const struct qmp_phy_init_tbl *txz;
|
|
int txz_num;
|
|
const struct qmp_phy_init_tbl *rxz;
|
|
int rxz_num;
|
|
const struct qmp_phy_init_tbl *pcs;
|
|
int pcs_num;
|
|
const struct qmp_phy_init_tbl *pcs_misc;
|
|
int pcs_misc_num;
|
|
const struct qmp_phy_init_tbl *pcs_lane1;
|
|
int pcs_lane1_num;
|
|
const struct qmp_phy_init_tbl *ln_shrd;
|
|
int ln_shrd_num;
|
|
};
|
|
|
|
/* struct qmp_phy_cfg - per-PHY initialization config */
|
|
struct qmp_phy_cfg {
|
|
int lanes;
|
|
|
|
const struct qmp_pcie_offsets *offsets;
|
|
|
|
/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
|
|
const struct qmp_phy_cfg_tbls tbls;
|
|
/*
|
|
* Additional init sequences for PHY blocks, providing additional
|
|
* register programming. They are used for providing separate sequences
|
|
* for the Root Complex and End Point use cases.
|
|
*
|
|
* If EP mode is not supported, both tables can be left unset.
|
|
*/
|
|
const struct qmp_phy_cfg_tbls *tbls_rc;
|
|
const struct qmp_phy_cfg_tbls *tbls_ep;
|
|
|
|
const struct qmp_phy_init_tbl *serdes_4ln_tbl;
|
|
int serdes_4ln_num;
|
|
|
|
/* resets to be requested */
|
|
const char * const *reset_list;
|
|
int num_resets;
|
|
/* regulators to be requested */
|
|
const char * const *vreg_list;
|
|
int num_vregs;
|
|
|
|
/* array of registers with different offsets */
|
|
const unsigned int *regs;
|
|
|
|
unsigned int pwrdn_ctrl;
|
|
/* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
|
|
unsigned int phy_status;
|
|
|
|
bool skip_start_delay;
|
|
|
|
/* QMP PHY pipe clock interface rate */
|
|
unsigned long pipe_clock_rate;
|
|
|
|
/* QMP PHY AUX clock interface rate */
|
|
unsigned long aux_clock_rate;
|
|
};
|
|
|
|
struct qmp_pcie {
|
|
struct device *dev;
|
|
|
|
const struct qmp_phy_cfg *cfg;
|
|
bool tcsr_4ln_config;
|
|
bool skip_init;
|
|
|
|
void __iomem *serdes;
|
|
void __iomem *pcs;
|
|
void __iomem *pcs_misc;
|
|
void __iomem *pcs_lane1;
|
|
void __iomem *tx;
|
|
void __iomem *rx;
|
|
void __iomem *tx2;
|
|
void __iomem *rx2;
|
|
void __iomem *txz;
|
|
void __iomem *rxz;
|
|
void __iomem *ln_shrd;
|
|
|
|
void __iomem *port_b;
|
|
|
|
struct clk_bulk_data *clks;
|
|
struct clk_bulk_data pipe_clks[2];
|
|
int num_pipe_clks;
|
|
|
|
struct reset_control_bulk_data *resets;
|
|
struct reset_control *nocsr_reset;
|
|
struct regulator_bulk_data *vregs;
|
|
|
|
struct phy *phy;
|
|
int mode;
|
|
|
|
struct clk_fixed_rate pipe_clk_fixed;
|
|
struct clk_fixed_rate aux_clk_fixed;
|
|
};
|
|
|
|
static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = readl(base + offset);
|
|
reg |= val;
|
|
writel(reg, base + offset);
|
|
|
|
/* ensure that above write is through */
|
|
readl(base + offset);
|
|
}
|
|
|
|
static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = readl(base + offset);
|
|
reg &= ~val;
|
|
writel(reg, base + offset);
|
|
|
|
/* ensure that above write is through */
|
|
readl(base + offset);
|
|
}
|
|
|
|
/* list of clocks required by phy */
|
|
static const char * const qmp_pciephy_clk_l[] = {
|
|
"aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux",
|
|
};
|
|
|
|
/* list of regulators */
|
|
static const char * const qmp_phy_vreg_l[] = {
|
|
"vdda-phy", "vdda-pll",
|
|
};
|
|
|
|
static const char * const sm8550_qmp_phy_vreg_l[] = {
|
|
"vdda-phy", "vdda-pll", "vdda-qref",
|
|
};
|
|
|
|
/* list of resets */
|
|
static const char * const ipq8074_pciephy_reset_l[] = {
|
|
"phy", "common",
|
|
};
|
|
|
|
static const char * const sdm845_pciephy_reset_l[] = {
|
|
"phy",
|
|
};
|
|
|
|
static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = {
|
|
.serdes = 0,
|
|
.pcs = 0x1800,
|
|
.tx = 0x0800,
|
|
/* no .rx for QHP */
|
|
};
|
|
|
|
static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = {
|
|
.serdes = 0,
|
|
.pcs = 0x0800,
|
|
.tx = 0x0200,
|
|
.rx = 0x0400,
|
|
};
|
|
|
|
static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = {
|
|
.serdes = 0,
|
|
.pcs = 0x0800,
|
|
.pcs_misc = 0x0600,
|
|
.tx = 0x0200,
|
|
.rx = 0x0400,
|
|
};
|
|
|
|
static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = {
|
|
.serdes = 0,
|
|
.pcs = 0x0800,
|
|
.pcs_misc = 0x0c00,
|
|
.tx = 0x0200,
|
|
.rx = 0x0400,
|
|
};
|
|
|
|
static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = {
|
|
.serdes = 0,
|
|
.pcs = 0x0a00,
|
|
.pcs_misc = 0x0e00,
|
|
.tx = 0x0200,
|
|
.rx = 0x0400,
|
|
.tx2 = 0x0600,
|
|
.rx2 = 0x0800,
|
|
};
|
|
|
|
static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = {
|
|
.serdes = 0x1000,
|
|
.pcs = 0x1200,
|
|
.pcs_misc = 0x1600,
|
|
.pcs_lane1 = 0x1e00,
|
|
.tx = 0x0000,
|
|
.rx = 0x0200,
|
|
.tx2 = 0x0800,
|
|
.rx2 = 0x0a00,
|
|
};
|
|
|
|
static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
|
|
.serdes = 0,
|
|
.pcs = 0x0200,
|
|
.pcs_misc = 0x0600,
|
|
.tx = 0x0e00,
|
|
.rx = 0x1000,
|
|
.tx2 = 0x1600,
|
|
.rx2 = 0x1800,
|
|
};
|
|
|
|
static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = {
|
|
.serdes = 0,
|
|
.pcs = 0x1000,
|
|
.pcs_misc = 0x1400,
|
|
.tx = 0x0200,
|
|
.rx = 0x0400,
|
|
.tx2 = 0x0600,
|
|
.rx2 = 0x0800,
|
|
};
|
|
|
|
static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = {
|
|
.serdes = 0x1000,
|
|
.pcs = 0x1200,
|
|
.pcs_misc = 0x1400,
|
|
.pcs_lane1 = 0x1e00,
|
|
.tx = 0x0000,
|
|
.rx = 0x0200,
|
|
.tx2 = 0x0800,
|
|
.rx2 = 0x0a00,
|
|
.ln_shrd = 0x0e00,
|
|
};
|
|
|
|
static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = {
|
|
.serdes = 0x2000,
|
|
.pcs = 0x2200,
|
|
.pcs_misc = 0x2400,
|
|
.tx = 0x0,
|
|
.rx = 0x0200,
|
|
.tx2 = 0x3800,
|
|
.rx2 = 0x3a00,
|
|
};
|
|
|
|
static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
|
|
.serdes = 0x1000,
|
|
.pcs = 0x1200,
|
|
.pcs_misc = 0x1400,
|
|
.tx = 0x0000,
|
|
.rx = 0x0200,
|
|
.tx2 = 0x0800,
|
|
.rx2 = 0x0a00,
|
|
.ln_shrd = 0x0e00,
|
|
};
|
|
|
|
static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_30 = {
|
|
.serdes = 0x8800,
|
|
.pcs = 0x9000,
|
|
.pcs_misc = 0x9800,
|
|
.tx = 0x0000,
|
|
.rx = 0x0200,
|
|
.txz = 0xe000,
|
|
.rxz = 0xe200,
|
|
.ln_shrd = 0x8000,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
|
|
.lanes = 1,
|
|
|
|
.offsets = &qmp_pcie_offsets_v2,
|
|
|
|
.tbls = {
|
|
.serdes = ipq8074_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
|
|
.tx = ipq8074_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
|
|
.rx = ipq8074_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
|
|
.pcs = ipq8074_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
|
|
},
|
|
.reset_list = ipq8074_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
|
|
.vreg_list = NULL,
|
|
.num_vregs = 0,
|
|
.regs = pciephy_v2_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
|
|
.lanes = 1,
|
|
|
|
.offsets = &qmp_pcie_offsets_v4x1,
|
|
|
|
.tbls = {
|
|
.serdes = ipq8074_pcie_gen3_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
|
|
.tx = ipq8074_pcie_gen3_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
|
|
.rx = ipq8074_pcie_gen3_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
|
|
.pcs = ipq8074_pcie_gen3_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
|
|
.pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl),
|
|
},
|
|
.reset_list = ipq8074_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
|
|
.vreg_list = NULL,
|
|
.num_vregs = 0,
|
|
.regs = pciephy_v4_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
|
|
.pipe_clock_rate = 250000000,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
|
|
.lanes = 1,
|
|
|
|
.offsets = &qmp_pcie_offsets_v4x1,
|
|
|
|
.tbls = {
|
|
.serdes = ipq6018_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
|
|
.tx = ipq6018_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
|
|
.rx = ipq6018_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
|
|
.pcs = ipq6018_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
|
|
.pcs_misc = ipq6018_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
|
|
},
|
|
.reset_list = ipq8074_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
|
|
.vreg_list = NULL,
|
|
.num_vregs = 0,
|
|
.regs = pciephy_v4_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = {
|
|
.lanes = 1,
|
|
|
|
.offsets = &qmp_pcie_offsets_v4x1,
|
|
|
|
.tbls = {
|
|
.serdes = ipq9574_gen3x1_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl),
|
|
.tx = ipq8074_pcie_gen3_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
|
|
.rx = ipq9574_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl),
|
|
.pcs = ipq9574_gen3x1_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl),
|
|
.pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl),
|
|
},
|
|
.reset_list = ipq8074_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
|
|
.vreg_list = NULL,
|
|
.num_vregs = 0,
|
|
.regs = pciephy_v4_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
.pipe_clock_rate = 250000000,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = {
|
|
.lanes = 2,
|
|
|
|
.offsets = &qmp_pcie_offsets_ipq9574,
|
|
|
|
.tbls = {
|
|
.serdes = ipq9574_gen3x2_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl),
|
|
.tx = ipq8074_pcie_gen3_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
|
|
.rx = ipq9574_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl),
|
|
.pcs = ipq9574_gen3x2_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_tbl),
|
|
.pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl),
|
|
},
|
|
.reset_list = ipq8074_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
|
|
.vreg_list = NULL,
|
|
.num_vregs = 0,
|
|
.regs = pciephy_v5_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
.pipe_clock_rate = 250000000,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg qcs615_pciephy_cfg = {
|
|
.lanes = 1,
|
|
|
|
.offsets = &qmp_pcie_offsets_v2,
|
|
|
|
.tbls = {
|
|
.serdes = qcs615_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(qcs615_pcie_serdes_tbl),
|
|
.tx = qcs615_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(qcs615_pcie_tx_tbl),
|
|
.rx = qcs615_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(qcs615_pcie_rx_tbl),
|
|
.pcs = qcs615_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(qcs615_pcie_pcs_tbl),
|
|
},
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v2_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg qcs8300_qmp_gen4x2_pciephy_cfg = {
|
|
.lanes = 2,
|
|
.offsets = &qmp_pcie_offsets_v5_20,
|
|
|
|
.tbls = {
|
|
.serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl,
|
|
.serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl),
|
|
.tx = sa8775p_qmp_gen4_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
|
|
.rx = qcs8300_qmp_gen4x2_pcie_rx_alt_tbl,
|
|
.rx_num = ARRAY_SIZE(qcs8300_qmp_gen4x2_pcie_rx_alt_tbl),
|
|
.pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl,
|
|
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl),
|
|
.pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl,
|
|
.serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl),
|
|
.pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
|
|
},
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v5_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS_4_20,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
|
|
.lanes = 1,
|
|
|
|
.offsets = &qmp_pcie_offsets_v3,
|
|
|
|
.tbls = {
|
|
.serdes = sdm845_qmp_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
|
|
.tx = sdm845_qmp_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
|
|
.rx = sdm845_qmp_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
|
|
.pcs = sdm845_qmp_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
|
|
.pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
|
|
},
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v3_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
|
|
.lanes = 1,
|
|
|
|
.offsets = &qmp_pcie_offsets_qhp,
|
|
|
|
.tbls = {
|
|
.serdes = sdm845_qhp_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
|
|
.tx = sdm845_qhp_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
|
|
.pcs = sdm845_qhp_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
|
|
},
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = sdm845_qhp_pciephy_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
|
|
.lanes = 1,
|
|
|
|
.offsets = &qmp_pcie_offsets_v4x1,
|
|
|
|
.tbls = {
|
|
.serdes = sm8250_qmp_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
|
|
.tx = sm8250_qmp_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
|
|
.rx = sm8250_qmp_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
|
|
.pcs = sm8250_qmp_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
|
|
.pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
|
|
},
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
|
|
.rx = sm8250_qmp_gen3x1_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
|
|
.pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
|
|
.pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
|
|
},
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v4_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
|
|
.lanes = 2,
|
|
|
|
.offsets = &qmp_pcie_offsets_v4x2,
|
|
|
|
.tbls = {
|
|
.serdes = sm8250_qmp_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
|
|
.tx = sm8250_qmp_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
|
|
.rx = sm8250_qmp_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
|
|
.pcs = sm8250_qmp_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
|
|
.pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
|
|
},
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.tx = sm8250_qmp_gen3x2_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
|
|
.rx = sm8250_qmp_gen3x2_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
|
|
.pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
|
|
.pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
|
|
},
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v4_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
|
|
.lanes = 1,
|
|
|
|
.offsets = &qmp_pcie_offsets_v3,
|
|
|
|
.tbls = {
|
|
.serdes = msm8998_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
|
|
.tx = msm8998_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
|
|
.rx = msm8998_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
|
|
.pcs = msm8998_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
|
|
},
|
|
.reset_list = ipq8074_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v3_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
|
|
.skip_start_delay = true,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sar2130p_qmp_gen3x2_pciephy_cfg = {
|
|
.lanes = 2,
|
|
|
|
.offsets = &qmp_pcie_offsets_v5,
|
|
|
|
.tbls = {
|
|
.tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
|
|
.rx = sm8550_qmp_gen3x2_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
|
|
.pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
|
|
.pcs_lane1 = sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl,
|
|
.pcs_lane1_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl),
|
|
},
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl),
|
|
.tx = sar2130p_qmp_gen3x2_pcie_rc_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_tx_tbl),
|
|
.pcs = sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl),
|
|
.pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
|
|
},
|
|
.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl),
|
|
.pcs = sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl),
|
|
.pcs_misc = sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl),
|
|
},
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v5_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
|
|
.lanes = 2,
|
|
|
|
.offsets = &qmp_pcie_offsets_v4x2,
|
|
|
|
.tbls = {
|
|
.serdes = sc8180x_qmp_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
|
|
.tx = sc8180x_qmp_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
|
|
.rx = sc8180x_qmp_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
|
|
.pcs = sc8180x_qmp_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
|
|
.pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
|
|
},
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v4_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = {
|
|
.lanes = 1,
|
|
|
|
.offsets = &qmp_pcie_offsets_v5,
|
|
|
|
.tbls = {
|
|
.serdes = sc8280xp_qmp_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
|
|
.tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl),
|
|
.rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl),
|
|
.pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl),
|
|
.pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl),
|
|
},
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v5_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = {
|
|
.lanes = 2,
|
|
|
|
.offsets = &qmp_pcie_offsets_v5,
|
|
|
|
.tbls = {
|
|
.serdes = sc8280xp_qmp_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
|
|
.tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
|
|
.rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
|
|
.pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
|
|
.pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
|
|
},
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v5_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = {
|
|
.lanes = 4,
|
|
|
|
.offsets = &qmp_pcie_offsets_v5,
|
|
|
|
.tbls = {
|
|
.serdes = sc8280xp_qmp_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
|
|
.tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
|
|
.rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
|
|
.pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
|
|
.pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
|
|
},
|
|
|
|
.serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl,
|
|
.serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl),
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v5_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
|
|
.lanes = 2,
|
|
|
|
.offsets = &qmp_pcie_offsets_v4_20,
|
|
|
|
.tbls = {
|
|
.serdes = sdx55_qmp_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
|
|
.tx = sdx55_qmp_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
|
|
.rx = sdx55_qmp_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
|
|
.pcs = sdx55_qmp_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
|
|
.pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sdx55_qmp_pcie_rc_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl),
|
|
.pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sdx55_qmp_pcie_ep_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl),
|
|
.pcs_lane1 = sdx55_qmp_pcie_ep_pcs_lane1_tbl,
|
|
.pcs_lane1_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_lane1_tbl),
|
|
},
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v4_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS_4_20,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
|
|
.lanes = 1,
|
|
|
|
.offsets = &qmp_pcie_offsets_v5,
|
|
|
|
.tbls = {
|
|
.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
|
|
.tx = sm8350_qmp_gen3x1_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),
|
|
.rx = sm8450_qmp_gen3_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
|
|
.pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
|
|
.pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
|
|
.rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),
|
|
},
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v5_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
|
|
.lanes = 2,
|
|
|
|
.offsets = &qmp_pcie_offsets_v5,
|
|
|
|
.tbls = {
|
|
.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
|
|
.tx = sm8350_qmp_gen3x2_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),
|
|
.rx = sm8450_qmp_gen3_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
|
|
.pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
|
|
.pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),
|
|
.pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),
|
|
},
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v5_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = {
|
|
.lanes = 2,
|
|
|
|
.offsets = &qmp_pcie_offsets_v6_20,
|
|
|
|
.tbls = {
|
|
.serdes = sdx65_qmp_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl),
|
|
.tx = sdx65_qmp_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl),
|
|
.rx = sdx65_qmp_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl),
|
|
.pcs = sdx65_qmp_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl),
|
|
.pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl),
|
|
.pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl,
|
|
.pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl),
|
|
},
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v6_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN,
|
|
.phy_status = PHYSTATUS_4_20,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
|
|
.lanes = 1,
|
|
|
|
.offsets = &qmp_pcie_offsets_v5,
|
|
|
|
.tbls = {
|
|
.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
|
|
.tx = sm8450_qmp_gen3x1_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
|
|
.rx = sm8450_qmp_gen3_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
|
|
.pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
|
|
.pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
|
|
.rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl),
|
|
},
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v5_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
|
|
.lanes = 2,
|
|
|
|
.offsets = &qmp_pcie_offsets_v5_20,
|
|
|
|
.tbls = {
|
|
.serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
|
|
.tx = sm8450_qmp_gen4x2_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
|
|
.rx = sm8450_qmp_gen4x2_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
|
|
.pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
|
|
.pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl),
|
|
.pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl),
|
|
.pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
|
|
},
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v5_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS_4_20,
|
|
|
|
/* 20MHz PHY AUX Clock */
|
|
.aux_clock_rate = 20000000,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {
|
|
.lanes = 2,
|
|
|
|
.offsets = &qmp_pcie_offsets_v5,
|
|
|
|
.tbls = {
|
|
.serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl),
|
|
.tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
|
|
.rx = sm8550_qmp_gen3x2_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
|
|
.pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
|
|
.pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
|
|
},
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v5_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
|
|
.lanes = 2,
|
|
|
|
.offsets = &qmp_pcie_offsets_v6_20,
|
|
|
|
.tbls = {
|
|
.serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
|
|
.tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
|
|
.rx = sm8550_qmp_gen4x2_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl),
|
|
.pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
|
|
.pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
|
|
.ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
|
|
.ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
|
|
},
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = sm8550_qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
|
|
.regs = pciephy_v6_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS_4_20,
|
|
|
|
/* 20MHz PHY AUX Clock */
|
|
.aux_clock_rate = 20000000,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = {
|
|
.lanes = 2,
|
|
|
|
.offsets = &qmp_pcie_offsets_v6_20,
|
|
|
|
.tbls = {
|
|
.serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
|
|
.tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
|
|
.rx = sm8650_qmp_gen4x2_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl),
|
|
.pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
|
|
.pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
|
|
.ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
|
|
.ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
|
|
},
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = sm8550_qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
|
|
.regs = pciephy_v6_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS_4_20,
|
|
|
|
/* 20MHz PHY AUX Clock */
|
|
.aux_clock_rate = 20000000,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {
|
|
.lanes = 2,
|
|
.offsets = &qmp_pcie_offsets_v5_20,
|
|
|
|
.tbls = {
|
|
.serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl,
|
|
.serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl),
|
|
.tx = sa8775p_qmp_gen4_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
|
|
.rx = sa8775p_qmp_gen4x2_pcie_rx_alt_tbl,
|
|
.rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl),
|
|
.pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl,
|
|
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl),
|
|
.pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
|
|
.pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl,
|
|
.pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl),
|
|
.ln_shrd = sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl,
|
|
.ln_shrd_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl),
|
|
|
|
},
|
|
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl,
|
|
.serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl),
|
|
.pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,
|
|
.serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),
|
|
.pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
|
|
.pcs = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl,
|
|
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl),
|
|
},
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v5_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS_4_20,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = {
|
|
.lanes = 4,
|
|
.offsets = &qmp_pcie_offsets_v5_30,
|
|
|
|
.tbls = {
|
|
.serdes = sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl,
|
|
.serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl),
|
|
.tx = sa8775p_qmp_gen4_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
|
|
.rx = sa8775p_qmp_gen4x4_pcie_rx_alt_tbl,
|
|
.rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl),
|
|
.pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl,
|
|
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl),
|
|
.pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl,
|
|
.serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl),
|
|
.pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
|
|
},
|
|
|
|
.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
|
|
.serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,
|
|
.serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),
|
|
.pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
|
|
},
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v5_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS_4_20,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = {
|
|
.lanes = 2,
|
|
|
|
.offsets = &qmp_pcie_offsets_v6_20,
|
|
|
|
.tbls = {
|
|
.serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl),
|
|
.tx = x1e80100_qmp_gen4x2_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl),
|
|
.rx = x1e80100_qmp_gen4x2_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl),
|
|
.pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl),
|
|
.pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl),
|
|
.ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl,
|
|
.ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl),
|
|
},
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v6_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS_4_20,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = {
|
|
.lanes = 4,
|
|
|
|
.offsets = &qmp_pcie_offsets_v6_20,
|
|
|
|
.tbls = {
|
|
.serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl),
|
|
.tx = x1e80100_qmp_gen4x2_pcie_tx_tbl,
|
|
.tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl),
|
|
.rx = x1e80100_qmp_gen4x2_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl),
|
|
.pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl),
|
|
.pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl),
|
|
.ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl,
|
|
.ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl),
|
|
},
|
|
|
|
.serdes_4ln_tbl = x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl,
|
|
.serdes_4ln_num = ARRAY_SIZE(x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl),
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v6_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS_4_20,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = {
|
|
.lanes = 8,
|
|
|
|
.offsets = &qmp_pcie_offsets_v6_30,
|
|
.tbls = {
|
|
.serdes = x1e80100_qmp_gen4x8_pcie_serdes_tbl,
|
|
.serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_serdes_tbl),
|
|
.rx = x1e80100_qmp_gen4x8_pcie_rx_tbl,
|
|
.rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rx_tbl),
|
|
.txz = x1e80100_qmp_gen4x8_pcie_txz_tbl,
|
|
.txz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_txz_tbl),
|
|
.rxz = x1e80100_qmp_gen4x8_pcie_rxz_tbl,
|
|
.rxz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rxz_tbl),
|
|
.pcs = x1e80100_qmp_gen4x8_pcie_pcs_tbl,
|
|
.pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_tbl),
|
|
.pcs_misc = x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl,
|
|
.pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl),
|
|
.ln_shrd = x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl,
|
|
.ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl),
|
|
},
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v6_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS_4_20,
|
|
};
|
|
|
|
static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = {
|
|
.lanes = 4,
|
|
|
|
.offsets = &qmp_pcie_offsets_v6_20,
|
|
|
|
.reset_list = sdm845_pciephy_reset_l,
|
|
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
|
|
.vreg_list = qmp_phy_vreg_l,
|
|
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
|
|
.regs = pciephy_v6_regs_layout,
|
|
|
|
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
|
|
.phy_status = PHYSTATUS_4_20,
|
|
};
|
|
|
|
static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
|
|
{
|
|
const struct qmp_phy_cfg *cfg = qmp->cfg;
|
|
const struct qmp_pcie_offsets *offs = cfg->offsets;
|
|
void __iomem *serdes, *tx3, *rx3, *tx4, *rx4, *pcs, *pcs_misc, *ln_shrd;
|
|
|
|
serdes = qmp->port_b + offs->serdes;
|
|
tx3 = qmp->port_b + offs->tx;
|
|
rx3 = qmp->port_b + offs->rx;
|
|
tx4 = qmp->port_b + offs->tx2;
|
|
rx4 = qmp->port_b + offs->rx2;
|
|
pcs = qmp->port_b + offs->pcs;
|
|
pcs_misc = qmp->port_b + offs->pcs_misc;
|
|
ln_shrd = qmp->port_b + offs->ln_shrd;
|
|
|
|
qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);
|
|
qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
|
|
|
|
qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1);
|
|
qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1);
|
|
|
|
qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2);
|
|
qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2);
|
|
|
|
qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);
|
|
qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
|
|
|
|
qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
|
|
}
|
|
|
|
static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
|
|
{
|
|
const struct qmp_phy_cfg *cfg = qmp->cfg;
|
|
void __iomem *serdes = qmp->serdes;
|
|
void __iomem *tx = qmp->tx;
|
|
void __iomem *rx = qmp->rx;
|
|
void __iomem *tx2 = qmp->tx2;
|
|
void __iomem *rx2 = qmp->rx2;
|
|
void __iomem *pcs = qmp->pcs;
|
|
void __iomem *pcs_misc = qmp->pcs_misc;
|
|
void __iomem *pcs_lane1 = qmp->pcs_lane1;
|
|
void __iomem *ln_shrd = qmp->ln_shrd;
|
|
|
|
if (!tbls)
|
|
return;
|
|
|
|
qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);
|
|
|
|
/*
|
|
* Tx/Rx registers that require different settings than
|
|
* txz/rxz must be programmed after txz/rxz.
|
|
*/
|
|
qmp_configure(qmp->dev, qmp->txz, tbls->txz, tbls->txz_num);
|
|
qmp_configure(qmp->dev, qmp->rxz, tbls->rxz, tbls->rxz_num);
|
|
|
|
qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1);
|
|
qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1);
|
|
|
|
if (cfg->lanes >= 2) {
|
|
qmp_configure_lane(qmp->dev, tx2, tbls->tx, tbls->tx_num, 2);
|
|
qmp_configure_lane(qmp->dev, rx2, tbls->rx, tbls->rx_num, 2);
|
|
}
|
|
|
|
qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);
|
|
qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
|
|
qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num);
|
|
|
|
if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
|
|
qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl,
|
|
cfg->serdes_4ln_num);
|
|
qmp_pcie_init_port_b(qmp, tbls);
|
|
}
|
|
|
|
qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
|
|
}
|
|
|
|
static int qmp_pcie_init(struct phy *phy)
|
|
{
|
|
struct qmp_pcie *qmp = phy_get_drvdata(phy);
|
|
const struct qmp_phy_cfg *cfg = qmp->cfg;
|
|
void __iomem *pcs = qmp->pcs;
|
|
bool phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL]));
|
|
int ret;
|
|
|
|
qmp->skip_init = qmp->nocsr_reset && phy_initialized;
|
|
/*
|
|
* We need to check the existence of init sequences in two cases:
|
|
* 1. The PHY doesn't support no_csr reset.
|
|
* 2. The PHY supports no_csr reset but isn't initialized by bootloader.
|
|
* As we can't skip init in these two cases.
|
|
*/
|
|
if (!qmp->skip_init && !cfg->tbls.serdes_num) {
|
|
dev_err(qmp->dev, "Init sequence not available\n");
|
|
return -ENODATA;
|
|
}
|
|
|
|
ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
|
|
if (ret) {
|
|
dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Toggle BCR reset for PHY that doesn't support no_csr reset or has not
|
|
* been initialized.
|
|
*/
|
|
if (!qmp->skip_init) {
|
|
ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
|
|
if (ret) {
|
|
dev_err(qmp->dev, "reset assert failed\n");
|
|
goto err_disable_regulators;
|
|
}
|
|
}
|
|
|
|
ret = reset_control_assert(qmp->nocsr_reset);
|
|
if (ret) {
|
|
dev_err(qmp->dev, "no-csr reset assert failed\n");
|
|
goto err_assert_reset;
|
|
}
|
|
|
|
usleep_range(200, 300);
|
|
|
|
if (!qmp->skip_init) {
|
|
ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
|
|
if (ret) {
|
|
dev_err(qmp->dev, "reset deassert failed\n");
|
|
goto err_assert_reset;
|
|
}
|
|
}
|
|
|
|
ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
|
|
if (ret)
|
|
goto err_assert_reset;
|
|
|
|
return 0;
|
|
|
|
err_assert_reset:
|
|
if (!qmp->skip_init)
|
|
reset_control_bulk_assert(cfg->num_resets, qmp->resets);
|
|
err_disable_regulators:
|
|
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int qmp_pcie_exit(struct phy *phy)
|
|
{
|
|
struct qmp_pcie *qmp = phy_get_drvdata(phy);
|
|
const struct qmp_phy_cfg *cfg = qmp->cfg;
|
|
|
|
if (qmp->nocsr_reset)
|
|
reset_control_assert(qmp->nocsr_reset);
|
|
else
|
|
reset_control_bulk_assert(cfg->num_resets, qmp->resets);
|
|
|
|
clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
|
|
|
|
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int qmp_pcie_power_on(struct phy *phy)
|
|
{
|
|
struct qmp_pcie *qmp = phy_get_drvdata(phy);
|
|
const struct qmp_phy_cfg *cfg = qmp->cfg;
|
|
const struct qmp_phy_cfg_tbls *mode_tbls;
|
|
void __iomem *pcs = qmp->pcs;
|
|
void __iomem *status;
|
|
unsigned int mask, val;
|
|
int ret;
|
|
|
|
/*
|
|
* Write CSR register for PHY that doesn't support no_csr reset or has not
|
|
* been initialized.
|
|
*/
|
|
if (qmp->skip_init)
|
|
goto skip_tbls_init;
|
|
|
|
qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
|
|
cfg->pwrdn_ctrl);
|
|
|
|
if (qmp->mode == PHY_MODE_PCIE_RC)
|
|
mode_tbls = cfg->tbls_rc;
|
|
else
|
|
mode_tbls = cfg->tbls_ep;
|
|
|
|
qmp_pcie_init_registers(qmp, &cfg->tbls);
|
|
qmp_pcie_init_registers(qmp, mode_tbls);
|
|
|
|
skip_tbls_init:
|
|
ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = reset_control_deassert(qmp->nocsr_reset);
|
|
if (ret) {
|
|
dev_err(qmp->dev, "no-csr reset deassert failed\n");
|
|
goto err_disable_pipe_clk;
|
|
}
|
|
|
|
if (qmp->skip_init)
|
|
goto skip_serdes_start;
|
|
|
|
/* Pull PHY out of reset state */
|
|
qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
|
|
|
|
/* start SerDes and Phy-Coding-Sublayer */
|
|
qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
|
|
|
|
if (!cfg->skip_start_delay)
|
|
usleep_range(1000, 1200);
|
|
|
|
skip_serdes_start:
|
|
status = pcs + cfg->regs[QPHY_PCS_STATUS];
|
|
mask = cfg->phy_status;
|
|
ret = readl_poll_timeout(status, val, !(val & mask), 200,
|
|
PHY_INIT_COMPLETE_TIMEOUT);
|
|
if (ret) {
|
|
dev_err(qmp->dev, "phy initialization timed-out\n");
|
|
goto err_disable_pipe_clk;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_disable_pipe_clk:
|
|
clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int qmp_pcie_power_off(struct phy *phy)
|
|
{
|
|
struct qmp_pcie *qmp = phy_get_drvdata(phy);
|
|
const struct qmp_phy_cfg *cfg = qmp->cfg;
|
|
|
|
clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
|
|
|
|
/*
|
|
* While powering off the PHY, only qmp->nocsr_reset needs to be checked. In
|
|
* this way, no matter whether the PHY settings were initially programmed by
|
|
* bootloader or PHY driver itself, we can reuse them when PHY is powered on
|
|
* next time.
|
|
*/
|
|
if (qmp->nocsr_reset)
|
|
goto skip_phy_deinit;
|
|
|
|
/* PHY reset */
|
|
qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
|
|
|
|
/* stop SerDes and Phy-Coding-Sublayer */
|
|
qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
|
|
SERDES_START | PCS_START);
|
|
|
|
/* Put PHY into POWER DOWN state: active low */
|
|
qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
|
|
cfg->pwrdn_ctrl);
|
|
|
|
skip_phy_deinit:
|
|
return 0;
|
|
}
|
|
|
|
static int qmp_pcie_enable(struct phy *phy)
|
|
{
|
|
int ret;
|
|
|
|
ret = qmp_pcie_init(phy);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = qmp_pcie_power_on(phy);
|
|
if (ret)
|
|
qmp_pcie_exit(phy);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int qmp_pcie_disable(struct phy *phy)
|
|
{
|
|
int ret;
|
|
|
|
ret = qmp_pcie_power_off(phy);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return qmp_pcie_exit(phy);
|
|
}
|
|
|
|
static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode)
|
|
{
|
|
struct qmp_pcie *qmp = phy_get_drvdata(phy);
|
|
|
|
switch (submode) {
|
|
case PHY_MODE_PCIE_RC:
|
|
case PHY_MODE_PCIE_EP:
|
|
qmp->mode = submode;
|
|
break;
|
|
default:
|
|
dev_err(&phy->dev, "Unsupported submode %d\n", submode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct phy_ops qmp_pcie_phy_ops = {
|
|
.power_on = qmp_pcie_enable,
|
|
.power_off = qmp_pcie_disable,
|
|
.set_mode = qmp_pcie_set_mode,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static int qmp_pcie_vreg_init(struct qmp_pcie *qmp)
|
|
{
|
|
const struct qmp_phy_cfg *cfg = qmp->cfg;
|
|
struct device *dev = qmp->dev;
|
|
int num = cfg->num_vregs;
|
|
int i;
|
|
|
|
qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
|
|
if (!qmp->vregs)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < num; i++)
|
|
qmp->vregs[i].supply = cfg->vreg_list[i];
|
|
|
|
return devm_regulator_bulk_get(dev, num, qmp->vregs);
|
|
}
|
|
|
|
static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
|
|
{
|
|
const struct qmp_phy_cfg *cfg = qmp->cfg;
|
|
struct device *dev = qmp->dev;
|
|
int i;
|
|
int ret;
|
|
|
|
qmp->resets = devm_kcalloc(dev, cfg->num_resets,
|
|
sizeof(*qmp->resets), GFP_KERNEL);
|
|
if (!qmp->resets)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < cfg->num_resets; i++)
|
|
qmp->resets[i].id = cfg->reset_list[i];
|
|
|
|
ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "failed to get resets\n");
|
|
|
|
qmp->nocsr_reset = devm_reset_control_get_optional_exclusive(dev, "phy_nocsr");
|
|
if (IS_ERR(qmp->nocsr_reset))
|
|
return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
|
|
"failed to get no-csr reset\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int qmp_pcie_clk_init(struct qmp_pcie *qmp)
|
|
{
|
|
struct device *dev = qmp->dev;
|
|
int num = ARRAY_SIZE(qmp_pciephy_clk_l);
|
|
int i;
|
|
|
|
qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
|
|
if (!qmp->clks)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < num; i++)
|
|
qmp->clks[i].id = qmp_pciephy_clk_l[i];
|
|
|
|
return devm_clk_bulk_get_optional(dev, num, qmp->clks);
|
|
}
|
|
|
|
static void phy_clk_release_provider(void *res)
|
|
{
|
|
of_clk_del_provider(res);
|
|
}
|
|
|
|
/*
|
|
* Register a fixed rate pipe clock.
|
|
*
|
|
* The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
|
|
* controls it. The <s>_pipe_clk coming out of the GCC is requested
|
|
* by the PHY driver for its operations.
|
|
* We register the <s>_pipe_clksrc here. The gcc driver takes care
|
|
* of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
|
|
* Below picture shows this relationship.
|
|
*
|
|
* +---------------+
|
|
* | PHY block |<<---------------------------------------+
|
|
* | | |
|
|
* | +-------+ | +-----+ |
|
|
* I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
|
|
* clk | +-------+ | +-----+
|
|
* +---------------+
|
|
*/
|
|
static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np)
|
|
{
|
|
struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
|
|
struct clk_init_data init = { };
|
|
int ret;
|
|
|
|
ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name);
|
|
if (ret) {
|
|
dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
|
|
return ret;
|
|
}
|
|
|
|
init.ops = &clk_fixed_rate_ops;
|
|
|
|
/*
|
|
* Controllers using QMP PHY-s use 125MHz pipe clock interface
|
|
* unless other frequency is specified in the PHY config.
|
|
*/
|
|
if (qmp->cfg->pipe_clock_rate)
|
|
fixed->fixed_rate = qmp->cfg->pipe_clock_rate;
|
|
else
|
|
fixed->fixed_rate = 125000000;
|
|
|
|
fixed->hw.init = &init;
|
|
|
|
return devm_clk_hw_register(qmp->dev, &fixed->hw);
|
|
}
|
|
|
|
/*
|
|
* Register a fixed rate PHY aux clock.
|
|
*
|
|
* The <s>_phy_aux_clksrc generated by PHY goes to the GCC that gate
|
|
* controls it. The <s>_phy_aux_clk coming out of the GCC is requested
|
|
* by the PHY driver for its operations.
|
|
* We register the <s>_phy_aux_clksrc here. The gcc driver takes care
|
|
* of assigning this <s>_phy_aux_clksrc as parent to <s>_phy_aux_clk.
|
|
* Below picture shows this relationship.
|
|
*
|
|
* +---------------+
|
|
* | PHY block |<<---------------------------------------------+
|
|
* | | |
|
|
* | +-------+ | +-----+ |
|
|
* I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+
|
|
* clk | +-------+ | +-----+
|
|
* +---------------+
|
|
*/
|
|
static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np)
|
|
{
|
|
struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed;
|
|
struct clk_init_data init = { };
|
|
char name[64];
|
|
|
|
snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev));
|
|
|
|
init.name = name;
|
|
init.ops = &clk_fixed_rate_ops;
|
|
|
|
fixed->fixed_rate = qmp->cfg->aux_clock_rate;
|
|
fixed->hw.init = &init;
|
|
|
|
return devm_clk_hw_register(qmp->dev, &fixed->hw);
|
|
}
|
|
|
|
static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec, void *data)
|
|
{
|
|
struct qmp_pcie *qmp = data;
|
|
|
|
/* Support legacy bindings */
|
|
if (!clkspec->args_count)
|
|
return &qmp->pipe_clk_fixed.hw;
|
|
|
|
switch (clkspec->args[0]) {
|
|
case QMP_PCIE_PIPE_CLK:
|
|
return &qmp->pipe_clk_fixed.hw;
|
|
case QMP_PCIE_PHY_AUX_CLK:
|
|
return &qmp->aux_clk_fixed.hw;
|
|
}
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np)
|
|
{
|
|
int ret;
|
|
|
|
ret = phy_pipe_clk_register(qmp, np);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (qmp->cfg->aux_clock_rate) {
|
|
ret = phy_aux_clk_register(qmp, np);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = of_clk_add_hw_provider(np, qmp_pcie_clk_hw_get, qmp);
|
|
if (ret)
|
|
return ret;
|
|
} else {
|
|
ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Roll a devm action because the clock provider is the child node, but
|
|
* the child node is not actually a device.
|
|
*/
|
|
return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
|
|
}
|
|
|
|
static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(qmp->dev);
|
|
const struct qmp_phy_cfg *cfg = qmp->cfg;
|
|
struct device *dev = qmp->dev;
|
|
struct clk *clk;
|
|
|
|
qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(qmp->serdes))
|
|
return PTR_ERR(qmp->serdes);
|
|
|
|
/*
|
|
* Get memory resources for the PHY:
|
|
* Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
|
|
* For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
|
|
* For single lane PHYs: pcs_misc (optional) -> 3.
|
|
*/
|
|
qmp->tx = devm_of_iomap(dev, np, 0, NULL);
|
|
if (IS_ERR(qmp->tx))
|
|
return PTR_ERR(qmp->tx);
|
|
|
|
if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy"))
|
|
qmp->rx = qmp->tx;
|
|
else
|
|
qmp->rx = devm_of_iomap(dev, np, 1, NULL);
|
|
if (IS_ERR(qmp->rx))
|
|
return PTR_ERR(qmp->rx);
|
|
|
|
qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
|
|
if (IS_ERR(qmp->pcs))
|
|
return PTR_ERR(qmp->pcs);
|
|
|
|
if (cfg->lanes >= 2) {
|
|
qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
|
|
if (IS_ERR(qmp->tx2))
|
|
return PTR_ERR(qmp->tx2);
|
|
|
|
qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
|
|
if (IS_ERR(qmp->rx2))
|
|
return PTR_ERR(qmp->rx2);
|
|
|
|
qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
|
|
} else {
|
|
qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
|
|
}
|
|
|
|
if (IS_ERR(qmp->pcs_misc) &&
|
|
of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
|
|
qmp->pcs_misc = qmp->pcs + 0x400;
|
|
|
|
if (IS_ERR(qmp->pcs_misc)) {
|
|
if (cfg->tbls.pcs_misc ||
|
|
(cfg->tbls_rc && cfg->tbls_rc->pcs_misc) ||
|
|
(cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) {
|
|
return PTR_ERR(qmp->pcs_misc);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* For all platforms where legacy bindings existed, PCS_LANE1 was
|
|
* mapped as a part of the PCS_MISC region.
|
|
*/
|
|
if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 != 0)
|
|
qmp->pcs_lane1 = qmp->pcs_misc +
|
|
(cfg->offsets->pcs_lane1 - cfg->offsets->pcs_misc);
|
|
|
|
clk = devm_get_clk_from_child(dev, np, NULL);
|
|
if (IS_ERR(clk)) {
|
|
return dev_err_probe(dev, PTR_ERR(clk),
|
|
"failed to get pipe clock\n");
|
|
}
|
|
|
|
qmp->num_pipe_clks = 1;
|
|
qmp->pipe_clks[0].id = "pipe";
|
|
qmp->pipe_clks[0].clk = clk;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp)
|
|
{
|
|
struct regmap *tcsr;
|
|
unsigned int args[2];
|
|
int ret;
|
|
|
|
tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node,
|
|
"qcom,4ln-config-sel",
|
|
ARRAY_SIZE(args), args);
|
|
if (IS_ERR(tcsr)) {
|
|
ret = PTR_ERR(tcsr);
|
|
if (ret == -ENOENT)
|
|
return 0;
|
|
|
|
dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = regmap_test_bits(tcsr, args[0], BIT(args[1]));
|
|
if (ret < 0) {
|
|
dev_err(qmp->dev, "failed to read tcsr: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
qmp->tcsr_4ln_config = ret;
|
|
|
|
dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(qmp->dev);
|
|
const struct qmp_phy_cfg *cfg = qmp->cfg;
|
|
const struct qmp_pcie_offsets *offs = cfg->offsets;
|
|
struct device *dev = qmp->dev;
|
|
void __iomem *base;
|
|
int ret;
|
|
|
|
if (!offs)
|
|
return -EINVAL;
|
|
|
|
ret = qmp_pcie_get_4ln_config(qmp);
|
|
if (ret)
|
|
return ret;
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
qmp->serdes = base + offs->serdes;
|
|
qmp->pcs = base + offs->pcs;
|
|
qmp->pcs_misc = base + offs->pcs_misc;
|
|
qmp->pcs_lane1 = base + offs->pcs_lane1;
|
|
qmp->tx = base + offs->tx;
|
|
qmp->rx = base + offs->rx;
|
|
|
|
if (cfg->lanes >= 2) {
|
|
qmp->tx2 = base + offs->tx2;
|
|
qmp->rx2 = base + offs->rx2;
|
|
}
|
|
|
|
if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
|
|
qmp->port_b = devm_platform_ioremap_resource(pdev, 1);
|
|
if (IS_ERR(qmp->port_b))
|
|
return PTR_ERR(qmp->port_b);
|
|
}
|
|
|
|
qmp->txz = base + offs->txz;
|
|
qmp->rxz = base + offs->rxz;
|
|
|
|
if (cfg->tbls.ln_shrd)
|
|
qmp->ln_shrd = base + offs->ln_shrd;
|
|
|
|
qmp->num_pipe_clks = 2;
|
|
qmp->pipe_clks[0].id = "pipe";
|
|
qmp->pipe_clks[1].id = "pipediv2";
|
|
|
|
ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int qmp_pcie_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct phy_provider *phy_provider;
|
|
struct device_node *np;
|
|
struct qmp_pcie *qmp;
|
|
int ret;
|
|
|
|
qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
|
|
if (!qmp)
|
|
return -ENOMEM;
|
|
|
|
qmp->dev = dev;
|
|
|
|
qmp->cfg = of_device_get_match_data(dev);
|
|
if (!qmp->cfg)
|
|
return -EINVAL;
|
|
|
|
WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);
|
|
WARN_ON_ONCE(!qmp->cfg->phy_status);
|
|
|
|
ret = qmp_pcie_clk_init(qmp);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = qmp_pcie_reset_init(qmp);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = qmp_pcie_vreg_init(qmp);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Check for legacy binding with child node. */
|
|
np = of_get_next_available_child(dev->of_node, NULL);
|
|
if (np) {
|
|
ret = qmp_pcie_parse_dt_legacy(qmp, np);
|
|
} else {
|
|
np = of_node_get(dev->of_node);
|
|
ret = qmp_pcie_parse_dt(qmp);
|
|
}
|
|
if (ret)
|
|
goto err_node_put;
|
|
|
|
ret = qmp_pcie_register_clocks(qmp, np);
|
|
if (ret)
|
|
goto err_node_put;
|
|
|
|
qmp->mode = PHY_MODE_PCIE_RC;
|
|
|
|
qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops);
|
|
if (IS_ERR(qmp->phy)) {
|
|
ret = PTR_ERR(qmp->phy);
|
|
dev_err(dev, "failed to create PHY: %d\n", ret);
|
|
goto err_node_put;
|
|
}
|
|
|
|
phy_set_drvdata(qmp->phy, qmp);
|
|
|
|
of_node_put(np);
|
|
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
|
|
|
return PTR_ERR_OR_ZERO(phy_provider);
|
|
|
|
err_node_put:
|
|
of_node_put(np);
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id qmp_pcie_of_match_table[] = {
|
|
{
|
|
.compatible = "qcom,ipq6018-qmp-pcie-phy",
|
|
.data = &ipq6018_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
|
|
.data = &ipq8074_pciephy_gen3_cfg,
|
|
}, {
|
|
.compatible = "qcom,ipq8074-qmp-pcie-phy",
|
|
.data = &ipq8074_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy",
|
|
.data = &ipq9574_gen3x1_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
|
|
.data = &ipq9574_gen3x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,msm8998-qmp-pcie-phy",
|
|
.data = &msm8998_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy",
|
|
.data = &qcs615_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy",
|
|
.data = &qcs8300_qmp_gen4x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
|
|
.data = &sa8775p_qmp_gen4x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
|
|
.data = &sa8775p_qmp_gen4x4_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy",
|
|
.data = &sar2130p_qmp_gen3x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sc8180x-qmp-pcie-phy",
|
|
.data = &sc8180x_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
|
|
.data = &sc8280xp_qmp_gen3x1_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
|
|
.data = &sc8280xp_qmp_gen3x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
|
|
.data = &sc8280xp_qmp_gen3x4_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sdm845-qhp-pcie-phy",
|
|
.data = &sdm845_qhp_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sdm845-qmp-pcie-phy",
|
|
.data = &sdm845_qmp_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sdx55-qmp-pcie-phy",
|
|
.data = &sdx55_qmp_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
|
|
.data = &sdx65_qmp_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
|
|
.data = &sm8250_qmp_gen3x1_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
|
|
.data = &sm8250_qmp_gen3x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
|
|
.data = &sm8250_qmp_gen3x1_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
|
|
.data = &sm8250_qmp_gen3x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sm8250-qmp-modem-pcie-phy",
|
|
.data = &sm8250_qmp_gen3x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
|
|
.data = &sm8350_qmp_gen3x1_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
|
|
.data = &sm8350_qmp_gen3x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
|
|
.data = &sm8450_qmp_gen3x1_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
|
|
.data = &sm8450_qmp_gen4x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
|
|
.data = &sm8550_qmp_gen3x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
|
|
.data = &sm8550_qmp_gen4x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy",
|
|
.data = &sm8550_qmp_gen3x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",
|
|
.data = &sm8650_qmp_gen4x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy",
|
|
.data = &sm8550_qmp_gen3x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",
|
|
.data = &x1e80100_qmp_gen4x2_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy",
|
|
.data = &x1e80100_qmp_gen4x4_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy",
|
|
.data = &x1e80100_qmp_gen4x8_pciephy_cfg,
|
|
}, {
|
|
.compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy",
|
|
.data = &qmp_v6_gen4x4_pciephy_cfg,
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table);
|
|
|
|
static struct platform_driver qmp_pcie_driver = {
|
|
.probe = qmp_pcie_probe,
|
|
.driver = {
|
|
.name = "qcom-qmp-pcie-phy",
|
|
.of_match_table = qmp_pcie_of_match_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(qmp_pcie_driver);
|
|
|
|
MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
|
|
MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver");
|
|
MODULE_LICENSE("GPL v2");
|