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The Coresight TMC Control Unit hosts miscellaneous configuration registers which control various features related to TMC ETR sink. Based on the trace ID, which is programmed in the related CTCU ATID register of a specific ETR, trace data with that trace ID gets into the ETR buffer, while other trace data gets dropped. Enabling source device sets one bit of the ATID register based on source device's trace ID. Disabling source device resets the bit according to the source device's trace ID. Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20250303032931.2500935-10-quic_jiegan@quicinc.com
39 lines
917 B
C
39 lines
917 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _CORESIGHT_CTCU_H
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#define _CORESIGHT_CTCU_H
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#include "coresight-trace-id.h"
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/* Maximum number of supported ETR devices for a single CTCU. */
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#define ETR_MAX_NUM 2
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/**
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* struct ctcu_etr_config
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* @atid_offset: offset to the ATID0 Register.
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* @port_num: in-port number of CTCU device that connected to ETR.
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*/
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struct ctcu_etr_config {
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const u32 atid_offset;
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const u32 port_num;
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};
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struct ctcu_config {
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const struct ctcu_etr_config *etr_cfgs;
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int num_etr_config;
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};
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struct ctcu_drvdata {
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void __iomem *base;
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struct clk *apb_clk;
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struct device *dev;
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struct coresight_device *csdev;
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raw_spinlock_t spin_lock;
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u32 atid_offset[ETR_MAX_NUM];
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/* refcnt for each traceid of each sink */
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u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP];
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};
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#endif
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