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40 lines
917 B
C
40 lines
917 B
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _CORESIGHT_CTCU_H
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#define _CORESIGHT_CTCU_H
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#include "coresight-trace-id.h"
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/* Maximum number of supported ETR devices for a single CTCU. */
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#define ETR_MAX_NUM 2
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/**
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* struct ctcu_etr_config
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* @atid_offset: offset to the ATID0 Register.
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* @port_num: in-port number of CTCU device that connected to ETR.
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*/
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struct ctcu_etr_config {
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const u32 atid_offset;
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const u32 port_num;
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};
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struct ctcu_config {
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const struct ctcu_etr_config *etr_cfgs;
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int num_etr_config;
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};
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struct ctcu_drvdata {
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void __iomem *base;
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struct clk *apb_clk;
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struct device *dev;
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struct coresight_device *csdev;
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raw_spinlock_t spin_lock;
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u32 atid_offset[ETR_MAX_NUM];
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/* refcnt for each traceid of each sink */
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u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP];
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};
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#endif
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