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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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2c7ad99255
Only needs to be supported for iopgtables mmu, the other cases are either only used for kernel managed mappings (where offset is always zero) or devices which do not support sparse bindings. Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Tested-by: Antonino Maniscalco <antomani103@gmail.com> Reviewed-by: Antonino Maniscalco <antomani103@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/661501/
122 lines
3 KiB
C
122 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2018 The Linux Foundation. All rights reserved. */
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#include <linux/dma-mapping.h>
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#include "msm_drv.h"
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#include "msm_mmu.h"
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#include "adreno_gpu.h"
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#include "a2xx_gpu.h"
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#include "a2xx.xml.h"
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struct a2xx_gpummu {
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struct msm_mmu base;
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struct msm_gpu *gpu;
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dma_addr_t pt_base;
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uint32_t *table;
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};
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#define to_a2xx_gpummu(x) container_of(x, struct a2xx_gpummu, base)
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#define GPUMMU_VA_START SZ_16M
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#define GPUMMU_VA_RANGE (0xfff * SZ_64K)
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#define GPUMMU_PAGE_SIZE SZ_4K
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#define TABLE_SIZE (sizeof(uint32_t) * GPUMMU_VA_RANGE / GPUMMU_PAGE_SIZE)
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static void a2xx_gpummu_detach(struct msm_mmu *mmu)
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{
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}
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static int a2xx_gpummu_map(struct msm_mmu *mmu, uint64_t iova,
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struct sg_table *sgt, size_t off, size_t len,
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int prot)
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{
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struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu);
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unsigned idx = (iova - GPUMMU_VA_START) / GPUMMU_PAGE_SIZE;
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struct sg_dma_page_iter dma_iter;
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unsigned prot_bits = 0;
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WARN_ON(off != 0);
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if (prot & IOMMU_WRITE)
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prot_bits |= 1;
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if (prot & IOMMU_READ)
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prot_bits |= 2;
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for_each_sgtable_dma_page(sgt, &dma_iter, 0) {
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dma_addr_t addr = sg_page_iter_dma_address(&dma_iter);
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int i;
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for (i = 0; i < PAGE_SIZE; i += GPUMMU_PAGE_SIZE)
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gpummu->table[idx++] = (addr + i) | prot_bits;
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}
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/* we can improve by deferring flush for multiple map() */
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gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE,
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL |
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC);
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return 0;
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}
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static int a2xx_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len)
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{
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struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu);
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unsigned idx = (iova - GPUMMU_VA_START) / GPUMMU_PAGE_SIZE;
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unsigned i;
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for (i = 0; i < len / GPUMMU_PAGE_SIZE; i++, idx++)
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gpummu->table[idx] = 0;
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gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE,
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL |
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC);
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return 0;
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}
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static void a2xx_gpummu_destroy(struct msm_mmu *mmu)
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{
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struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu);
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dma_free_attrs(mmu->dev, TABLE_SIZE, gpummu->table, gpummu->pt_base,
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DMA_ATTR_FORCE_CONTIGUOUS);
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kfree(gpummu);
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}
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static const struct msm_mmu_funcs funcs = {
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.detach = a2xx_gpummu_detach,
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.map = a2xx_gpummu_map,
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.unmap = a2xx_gpummu_unmap,
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.destroy = a2xx_gpummu_destroy,
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};
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struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu)
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{
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struct a2xx_gpummu *gpummu;
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gpummu = kzalloc(sizeof(*gpummu), GFP_KERNEL);
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if (!gpummu)
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return ERR_PTR(-ENOMEM);
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gpummu->table = dma_alloc_attrs(dev, TABLE_SIZE + 32, &gpummu->pt_base,
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GFP_KERNEL | __GFP_ZERO, DMA_ATTR_FORCE_CONTIGUOUS);
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if (!gpummu->table) {
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kfree(gpummu);
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return ERR_PTR(-ENOMEM);
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}
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gpummu->gpu = gpu;
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msm_mmu_init(&gpummu->base, dev, &funcs, MSM_MMU_GPUMMU);
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return &gpummu->base;
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}
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void a2xx_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
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dma_addr_t *tran_error)
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{
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dma_addr_t base = to_a2xx_gpummu(mmu)->pt_base;
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*pt_base = base;
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*tran_error = base + TABLE_SIZE; /* 32-byte aligned */
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}
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