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Enable the minimal blocks required for booting the Renesas RZ/Five SMARC EVK with initramfs. Below are the blocks which are enabled: - CPG - CPU0 - DDR (memory regions) - PINCTRL - PLIC - SCIF0 As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and carrier [2] board DTSIs which enables almost all the blocks supported by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually enabling the blocks hence the aliases for ETH/I2C are deleted and rest of the IP blocks are marked as disabled/deleted. [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi [2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20221028165921.94487-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
27 lines
681 B
Text
27 lines
681 B
Text
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/Five SMARC EVK
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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/dts-v1/;
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/*
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* DIP-Switch SW1 setting
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* 1 : High; 0: Low
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* SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
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* SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
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* Please change below macros according to SW1 setting on the SoM
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*/
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#define SW_SW0_DEV_SEL 1
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#define SW_ET0_EN_N 1
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#include "r9a07g043f.dtsi"
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#include "rzfive-smarc-som.dtsi"
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#include "rzfive-smarc.dtsi"
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/ {
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model = "Renesas SMARC EVK based on r9a07g043f01";
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compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
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};
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