linux/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
Niravkumar L Rabara 17d321d4a0 arm64: dts: socfpga: agilex5: add led and memory nodes
Add LED and memory nodes, and enabled GPIO0 for Agilex5 devkit.

Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-03-26 06:47:04 -05:00

90 lines
1.3 KiB
Text

// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2023, Intel Corporation
*/
#include "socfpga_agilex5.dtsi"
/ {
model = "SoCFPGA Agilex5 SoCDK";
compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
label = "hps_led0";
gpios = <&porta 11 GPIO_ACTIVE_HIGH>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0x0 0x80000000 0x0 0x0>;
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&osc1 {
clock-frequency = <25000000>;
};
&qspi {
status = "okay";
flash@0 {
compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,read-delay = <2>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
qspi_boot: partition@0 {
label = "u-boot";
reg = <0x0 0x04200000>;
};
root: partition@4200000 {
label = "root";
reg = <0x04200000 0x0be00000>;
};
};
};
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
disable-over-current;
};
&watchdog0 {
status = "okay";
};