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The iMX8QXP and iMX8QM have a CAAM (Cryptographic Acceleration and Assurance Module) like many other iMXs. Add the definitions for it. Job Rings 0 and 1 are bound to the SECO (Security Controller) ARM core and are not exposed outside it. There's no point to define them in the bindings as they cannot be used outside the SECO. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: John Ernberg <john.ernberg@actia.se> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
38 lines
1,000 B
Text
38 lines
1,000 B
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <dt-bindings/firmware/imx/rsrc.h>
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security_subsys: bus@31400000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x31400000 0x0 0x31400000 0x90000>;
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crypto: crypto@31400000 {
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compatible = "fsl,imx8qm-caam", "fsl,sec-v4.0";
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reg = <0x31400000 0x90000>;
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x31400000 0x90000>;
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power-domains = <&pd IMX_SC_R_CAAM_JR2>;
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fsl,sec-era = <9>;
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sec_jr2: jr@30000 {
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compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring";
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reg = <0x30000 0x10000>;
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interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&pd IMX_SC_R_CAAM_JR2>;
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};
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sec_jr3: jr@40000 {
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compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring";
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reg = <0x40000 0x10000>;
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interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&pd IMX_SC_R_CAAM_JR3>;
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};
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};
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};
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