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arm64: dts: freescale: imx8qxp/imx8qm: Add CAAM support

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The iMX8QXP and iMX8QM have a CAAM (Cryptographic Acceleration and
Assurance Module) like many other iMXs.

Add the definitions for it.

Job Rings 0 and 1 are bound to the SECO (Security Controller) ARM core
and are not exposed outside it. There's no point to define them in the
bindings as they cannot be used outside the SECO.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: John Ernberg <john.ernberg@actia.se>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Horia Geantă 2025-06-11 11:38:09 +00:00 • committed by Shawn Guo
parent fc0d2840a0
commit 5da259600d
4 changed files with 57 additions and 0 deletions
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38
arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi Normal file
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@ -0,0 +1,38 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
#include <dt-bindings/firmware/imx/rsrc.h>
security_subsys: bus@31400000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x31400000 0x0 0x31400000 0x90000>;
crypto: crypto@31400000 {
compatible = "fsl,imx8qm-caam", "fsl,sec-v4.0";
reg = <0x31400000 0x90000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x31400000 0x90000>;
power-domains = <&pd IMX_SC_R_CAAM_JR2>;
fsl,sec-era = <9>;
sec_jr2: jr@30000 {
compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_CAAM_JR2>;
};
sec_jr3: jr@40000 {
compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_CAAM_JR3>;
};
};
};

1
arch/arm64/boot/dts/freescale/imx8qm.dtsi
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@ -617,6 +617,7 @@
};
/* sorted in register address */
#include "imx8-ss-security.dtsi"
#include "imx8-ss-cm41.dtsi"
#include "imx8-ss-audio.dtsi"
#include "imx8-ss-vpu.dtsi"

16
arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 Actia Nordic AB
*/
&crypto {
compatible = "fsl,imx8qxp-caam", "fsl,sec-v4.0";
};
&sec_jr2 {
compatible = "fsl,imx8qxp-job-ring", "fsl,sec-v4.0-job-ring";
};
&sec_jr3 {
compatible = "fsl,imx8qxp-job-ring", "fsl,sec-v4.0-job-ring";
};

2
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
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@ -321,6 +321,7 @@
/* sorted in register address */
#include "imx8-ss-img.dtsi"
#include "imx8-ss-vpu.dtsi"
#include "imx8-ss-security.dtsi"
#include "imx8-ss-cm40.dtsi"
#include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-adma.dtsi"
@ -332,6 +333,7 @@
#include "imx8qxp-ss-img.dtsi"
#include "imx8qxp-ss-vpu.dtsi"
#include "imx8qxp-ss-security.dtsi"
#include "imx8qxp-ss-adma.dtsi"
#include "imx8qxp-ss-conn.dtsi"
#include "imx8qxp-ss-lsio.dtsi"