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0c56228119
There's no need include the CPU number in the L2 cache node names as the names are local to the CPU nodes. The documented node name is also just "l2-cache". The L3 cache is not part of cpu@0/l2-cache as it is shared among all cores. Move it to /cpus node which is the typical place for shared caches. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250403-dt-cpu-schema-v1-3-076be7171a85@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
323 lines
6.9 KiB
Text
323 lines
6.9 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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soc_refclk50mhz: clock-50000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "apb_pclk";
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};
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soc_refclk85mhz: clock-85000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <85000000>;
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clock-output-names = "iofpga:aclk";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,rainier";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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/* 4 ways set associative */
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i-cache-size = <0x10000>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_0>;
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clocks = <&scmi_dvfs 0>;
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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/* 8 ways set associative */
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu1: cpu@100 {
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compatible = "arm,rainier";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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/* 4 ways set associative */
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i-cache-size = <0x10000>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_1>;
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clocks = <&scmi_dvfs 0>;
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l2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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/* 8 ways set associative */
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu2: cpu@10000 {
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compatible = "arm,rainier";
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reg = <0x0 0x10000>;
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device_type = "cpu";
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enable-method = "psci";
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/* 4 ways set associative */
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i-cache-size = <0x10000>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_2>;
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clocks = <&scmi_dvfs 1>;
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l2_2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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/* 8 ways set associative */
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu3: cpu@10100 {
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compatible = "arm,rainier";
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reg = <0x0 0x10100>;
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device_type = "cpu";
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enable-method = "psci";
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/* 4 ways set associative */
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i-cache-size = <0x10000>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_3>;
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clocks = <&scmi_dvfs 1>;
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l2_3: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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/* 8 ways set associative */
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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l3_0: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-size = <0x100000>;
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cache-unified;
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};
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};
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firmware {
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interrupt-parent = <&gic>;
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scmi {
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compatible = "arm,scmi";
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mbox-names = "tx", "rx";
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mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
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shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_dvfs: protocol@13 {
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reg = <0x13>;
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#clock-cells = <1>;
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};
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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};
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/* The first bank of memory, memory map is actually provided by UEFI. */
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memory@80000000 {
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device_type = "memory";
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/* [0x80000000-0xffffffff] */
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reg = <0x00000000 0x80000000 0x0 0x7f000000>;
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};
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memory@8080000000 {
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device_type = "memory";
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/* [0x8080000000-0x83f7ffffff] */
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reg = <0x00000080 0x80000000 0x3 0x78000000>;
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};
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pmu {
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compatible = "arm,rainier-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure-firmware@ff000000 {
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reg = <0x0 0xff000000 0x0 0x01000000>;
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no-map;
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};
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};
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spe-pmu {
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compatible = "arm,statistical-profiling-extension-v1";
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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ranges;
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uart0: serial@2a400000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x2a400000 0x0 0x1000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_refclk50mhz>, <&soc_refclk50mhz>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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gic: interrupt-controller@30000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x30000000 0x0 0x10000>, /* GICD */
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<0x0 0x300c0000 0x0 0x80000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <3>;
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interrupt-controller;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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its1: msi-controller@30040000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x30040000 0x0 0x20000>;
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msi-controller;
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#msi-cells = <1>;
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};
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its2: msi-controller@30060000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x30060000 0x0 0x20000>;
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msi-controller;
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#msi-cells = <1>;
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};
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its_ccix: msi-controller@30080000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x30080000 0x0 0x20000>;
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msi-controller;
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#msi-cells = <1>;
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};
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its_pcie: msi-controller@300a0000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x300a0000 0x0 0x20000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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smmu_dp: iommu@2ce00000 {
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compatible = "arm,smmu-v3";
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reg = <0x0 0x2ce00000 0x0 0x40000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror", "cmdq-sync";
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#iommu-cells = <1>;
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};
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mailbox: mhu@45000000 {
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compatible = "arm,mhu-doorbell", "arm,primecell";
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reg = <0x0 0x45000000 0x0 0x1000>;
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interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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clocks = <&soc_refclk50mhz>;
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clock-names = "apb_pclk";
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};
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sram: sram@6000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x06000000 0x0 0x8000>;
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ranges = <0 0x0 0x06000000 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpu_scp_hpri0: scp-sram@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x80>;
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};
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cpu_scp_hpri1: scp-sram@80 {
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compatible = "arm,scmi-shmem";
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reg = <0x80 0x80>;
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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