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arm64: dts: morello: Fix-up cache nodes

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There's no need include the CPU number in the L2 cache node names as
the names are local to the CPU nodes. The documented node name is
also just "l2-cache".

The L3 cache is not part of cpu@0/l2-cache as it is shared among all
cores. Move it to /cpus node which is the typical place for shared
caches.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20250403-dt-cpu-schema-v1-3-076be7171a85@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This commit is contained in:
Rob Herring (Arm) 2025-04-03 21:59:24 -05:00 • committed by Sudeep Holla
parent 0af2f6be1b
commit 0c56228119
1 changed files with 11 additions and 11 deletions
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22
arch/arm64/boot/dts/arm/morello.dtsi
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@ -44,7 +44,7 @@
next-level-cache = <&l2_0>;
clocks = <&scmi_dvfs 0>;
l2_0: l2-cache-0 {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
/* 8 ways set associative */
@ -53,13 +53,6 @@
cache-sets = <2048>;
cache-unified;
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-size = <0x100000>;
cache-unified;
};
};
};
@ -78,7 +71,7 @@
next-level-cache = <&l2_1>;
clocks = <&scmi_dvfs 0>;
l2_1: l2-cache-1 {
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
/* 8 ways set associative */
@ -105,7 +98,7 @@
next-level-cache = <&l2_2>;
clocks = <&scmi_dvfs 1>;
l2_2: l2-cache-2 {
l2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
/* 8 ways set associative */
@ -132,7 +125,7 @@
next-level-cache = <&l2_3>;
clocks = <&scmi_dvfs 1>;
l2_3: l2-cache-3 {
l2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
/* 8 ways set associative */
@ -143,6 +136,13 @@
next-level-cache = <&l3_0>;
};
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-size = <0x100000>;
cache-unified;
};
};
firmware {