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Each TAD provides eight 64-bit counters for monitoring cache behavior.The driver always configures the same counter for all the TADs. The user would end up effectively reserving one of eight counters in every TAD to look across all TADs. The occurrences of events are aggregated and presented to the user at the end of running the workload. The driver does not provide a way for the user to partition TADs so that different TADs are used for different applications. The performance events reflect various internal or interface activities. By combining the values from multiple performance counters, cache performance can be measured in terms such as: cache miss rate, cache allocations, interface retry rate, internal resource occupancy, etc. Each supported counter's event and formatting information is exposed to sysfs at /sys/devices/tad/. Use perf tool stat command to measure the pmu events. For instance: perf stat -e tad_hit_ltg,tad_hit_dtg <workload> Signed-off-by: Gowthami Thiagarajan <gthiagarajan@marvell.com> Link: https://lore.kernel.org/r/20241108040619.753343-6-gthiagarajan@marvell.com Signed-off-by: Will Deacon <will@kernel.org>
31 lines
485 B
ReStructuredText
31 lines
485 B
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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===========================
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Performance monitor support
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===========================
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.. toctree::
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:maxdepth: 1
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hisi-pmu
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hisi-pcie-pmu
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hns3-pmu
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imx-ddr
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qcom_l2_pmu
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qcom_l3_pmu
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starfive_starlink_pmu
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mrvl-odyssey-ddr-pmu
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mrvl-odyssey-tad-pmu
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arm-ccn
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arm-cmn
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arm-ni
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xgene-pmu
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arm_dsu_pmu
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thunderx2-pmu
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alibaba_pmu
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dwc_pcie_pmu
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nvidia-pmu
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meson-ddr-pmu
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cxl
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ampere_cspmu
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mrvl-pem-pmu
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