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linux/Documentation/admin-guide/perf/index.rst

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docs: add SPDX tags to new index files All those new files I added are under GPL v2.0 license. Add the corresponding SPDX headers to them. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2019-06-28 07:13:34 -03:00
.. SPDX-License-Identifier: GPL-2.0
docs: perf: convert to ReST Rename the perf documentation files to ReST, add an index for them and adjust in order to produce a nice html output via the Sphinx build system. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2019-04-18 17:35:40 -03:00
===========================
Performance monitor support
===========================
.. toctree::
:maxdepth: 1
hisi-pmu
docs: fix 'make htmldocs' warning in perf Fix following 'make htmldocs' warnings: ./Documentation/admin-guide/perf/hisi-pcie-pmu.rst: WARNING: document isn't included in any toctree Fixes: c8602008e247 ("docs: perf: Add description for HiSilicon PCIe PMU driver") Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Reviewed-by: John Garry <john.garry@huawei.com> Link: https://lore.kernel.org/r/20220228031700.1669086-1-wanjiabing@vivo.com Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2022-02-28 11:16:56 +08:00
hisi-pcie-pmu
docs: perf: Include hns3-pmu.rst in toctree to fix 'htmldocs' WARNING After commit 39915b6b5fc2 ("drivers/perf: hisi: Add description for HNS3 PMU driver"),building the 'htmldocs' target results in the following warning: | Documentation/admin-guide/perf/hns3-pmu.rst: WARNING: document isn't included in any toctree Add 'hns3-pmu' to the perf toctree to silence the warning. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Will Deacon <will@kernel.org>
2022-07-07 11:25:40 +01:00
hns3-pmu
docs: perf: Add imx-ddr to documentation index Sphinx is currently outputting a warning where the file 'imx-ddr.rst' is not included in the documentation index. Additionally, the code highlighting and doc formatting can be slightly improved. Signed-off-by: Adam Zerella <adam.zerella@gmail.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2019-09-15 18:20:10 +10:00
imx-ddr
docs: perf: convert to ReST Rename the perf documentation files to ReST, add an index for them and adjust in order to produce a nice html output via the Sphinx build system. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2019-04-18 17:35:40 -03:00
qcom_l2_pmu
qcom_l3_pmu
docs: perf: Add description for StarFive's StarLink PMU StarFive StarLink PMU support monitoring L3 memory system PMU events. Add documentation to describe StarFive StarLink PMU support and it's usage. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com> Link: https://lore.kernel.org/r/20240229072720.3987876-4-jisheng.teoh@starfivetech.com Signed-off-by: Will Deacon <will@kernel.org>
2024-02-29 15:27:19 +08:00
starfive_starlink_pmu
perf/marvell: Odyssey DDR Performance monitor support Odyssey DRAM Subsystem supports eight counters for monitoring performance and software can program those counters to monitor any of the defined performance events. Supported performance events include those counted at the interface between the DDR controller and the PHY, interface between the DDR Controller and the CHI interconnect, or within the DDR Controller. Additionally DSS also supports two fixed performance event counters, one for ddr reads and the other for ddr writes. Signed-off-by: Gowthami Thiagarajan <gthiagarajan@marvell.com> Link: https://lore.kernel.org/r/20241108040619.753343-4-gthiagarajan@marvell.com Signed-off-by: Will Deacon <will@kernel.org>
2024-11-08 09:36:17 +05:30
mrvl-odyssey-ddr-pmu
perf/marvell: Odyssey LLC-TAD performance monitor support Each TAD provides eight 64-bit counters for monitoring cache behavior.The driver always configures the same counter for all the TADs. The user would end up effectively reserving one of eight counters in every TAD to look across all TADs. The occurrences of events are aggregated and presented to the user at the end of running the workload. The driver does not provide a way for the user to partition TADs so that different TADs are used for different applications. The performance events reflect various internal or interface activities. By combining the values from multiple performance counters, cache performance can be measured in terms such as: cache miss rate, cache allocations, interface retry rate, internal resource occupancy, etc. Each supported counter's event and formatting information is exposed to sysfs at /sys/devices/tad/. Use perf tool stat command to measure the pmu events. For instance: perf stat -e tad_hit_ltg,tad_hit_dtg <workload> Signed-off-by: Gowthami Thiagarajan <gthiagarajan@marvell.com> Link: https://lore.kernel.org/r/20241108040619.753343-6-gthiagarajan@marvell.com Signed-off-by: Will Deacon <will@kernel.org>
2024-11-08 09:36:19 +05:30
mrvl-odyssey-tad-pmu
docs: perf: convert to ReST Rename the perf documentation files to ReST, add an index for them and adjust in order to produce a nice html output via the Sphinx build system. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2019-04-18 17:35:40 -03:00
arm-ccn
perf: Add Arm CMN-600 PMU driver Initial driver for PMU event counting on the Arm CMN-600 interconnect. CMN sports an obnoxiously complex distributed PMU system as part of its debug and trace features, which can do all manner of things like sampling, cross-triggering and generating CoreSight trace. This driver covers the PMU functionality, plus the relevant aspects of watchpoints for simply counting matching flits. Tested-by: Tsahi Zidenberg <tsahee@amazon.com> Tested-by: Tuan Phan <tuanphan@os.amperecomputing.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
2020-09-18 14:28:38 +01:00
arm-cmn
perf: Add driver for Arm NI-700 interconnect PMU The Arm NI-700 Network-on-Chip Interconnect has a relatively straightforward design with a hierarchy of voltage, power, and clock domains, where each clock domain then contains a number of interface units and a PMU which can monitor events thereon. As such, it begets a relatively straightforward driver to interface those PMUs with perf. Even more so than with arm-cmn, users will require detailed knowledge of the wider system topology in order to meaningfully analyse anything, since the interconnect itself cannot know what lies beyond the boundary of each inscrutably-numbered interface. Given that, for now they are also expected to refer to the NI-700 documentation for the relevant event IDs to provide as well. An identifier is implemented so we can come back and add jevents if anyone really wants to. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/9933058d0ab8138c78a61cd6852ea5d5ff48e393.1725470837.git.robin.murphy@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2024-09-04 18:34:03 +01:00
arm-ni
docs: perf: convert to ReST Rename the perf documentation files to ReST, add an index for them and adjust in order to produce a nice html output via the Sphinx build system. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2019-04-18 17:35:40 -03:00
xgene-pmu
arm_dsu_pmu
thunderx2-pmu
docs: perf: Add description for Alibaba's T-Head PMU driver Alibaba's T-Head SoC implements uncore PMU for performance and functional debugging to facilitate system maintenance. Document it to provide guidance on how to use it. Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com> Link: https://lore.kernel.org/r/20220914022326.88550-2-xueshuai@linux.alibaba.com Signed-off-by: Will Deacon <will@kernel.org>
2022-09-14 10:23:24 +08:00
alibaba_pmu
docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Alibaba's T-Head Yitan 710 SoC includes Synopsys' DesignWare Core PCIe controller which implements PMU for performance and functional debugging to facilitate system maintenance. Document it to provide guidance on how to use it. Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com> Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Yicong Yang <yangyicong@hisilicon.com> Tested-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Link: https://lore.kernel.org/r/20231208025652.87192-2-xueshuai@linux.alibaba.com Signed-off-by: Will Deacon <will@kernel.org>
2023-12-08 10:56:48 +08:00
dwc_pcie_pmu
perf: arm_cspmu: Add support for NVIDIA SCF and MCF attribute Add support for NVIDIA System Cache Fabric (SCF) and Memory Control Fabric (MCF) PMU attributes for CoreSight PMU implementation in NVIDIA devices. Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Link: https://lore.kernel.org/r/20221111222330.48602-3-bwicaksono@nvidia.com Signed-off-by: Will Deacon <will@kernel.org>
2022-11-11 16:23:29 -06:00
nvidia-pmu
docs/perf: Add documentation for the Amlogic G12 DDR PMU Add a user guide to show how to use DDR PMU to monitor DDR bandwidth on Amlogic G12 SoC Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com> Reviewed-by: Chris Healy <healych@amazon.com> Link: https://lore.kernel.org/r/20221121021602.3306998-2-jiucheng.xu@amlogic.com Signed-off-by: Will Deacon <will@kernel.org>
2022-11-21 10:15:59 +08:00
meson-ddr-pmu
docs: perf: Minimal introduction the the CXL PMU device and driver Very basic introduction to the device and the current driver support provided. I expect to expand on this in future versions of this patch set. Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20230526095824.16336-6-Jonathan.Cameron@huawei.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2023-05-26 10:58:24 +01:00
cxl
docs/perf: Add ampere_cspmu to toctree to fix a build warning Add ampere_cspmu to toctree in order to address the following warning produced when building documents: Documentation/admin-guide/perf/ampere_cspmu.rst: WARNING: document isn't included in any toctree Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Closes: https://lore.kernel.org/all/20231011172250.5a6498e5@canb.auug.org.au/ Fixes: 53a810ad3c5c ("perf: arm_cspmu: ampere_cspmu: Add support for Ampere SoC PMU") Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Link: https://lore.kernel.org/r/20231012074103.3772114-1-ilkka@os.amperecomputing.com Signed-off-by: Will Deacon <will@kernel.org>
2023-10-12 00:41:03 -07:00
ampere_cspmu
perf/marvell: Marvell PEM performance monitor support PCI Express Interface PMU includes various performance counters to monitor the data that is transmitted over the PCIe link. The counters track various inbound and outbound transactions which includes separate counters for posted/non-posted/completion TLPs. Also, inbound and outbound memory read requests along with their latencies can also be monitored. Address Translation Services(ATS)events such as ATS Translation, ATS Page Request, ATS Invalidation along with their corresponding latencies are also supported. The performance counters are 64 bits wide. For instance, perf stat -e ib_tlp_pr <workload> tracks the inbound posted TLPs for the workload. Co-developed-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Gowthami Thiagarajan <gthiagarajan@marvell.com> Link: https://lore.kernel.org/r/20241028055309.17893-1-gthiagarajan@marvell.com Signed-off-by: Will Deacon <will@kernel.org>
2024-10-28 11:23:09 +05:30
mrvl-pem-pmu
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