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Add the debugfs property to provide a view of the current link's LTSSM status from the Root Port device. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by: Niklas Cassel <cassel@kernel.org> Tested-by: Hrishikesh Deleep <hrishikesh.d@samsung.com> Link: https://lore.kernel.org/r/20250223141848.231232-1-18255117159@163.com [kwilczynski: commit log, refactor dw_ltssm_sts_string() to avoid compilation errors on platforms that do not set CONFIG_PCIE_DW_HOST] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
157 lines
6 KiB
Text
157 lines
6 KiB
Text
What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_debug/lane_detect
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Date: February 2025
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Contact: Shradha Todi <shradha.t@samsung.com>
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Description: (RW) Write the lane number to be checked for detection. Read
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will return whether PHY indicates receiver detection on the
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selected lane. The default selected lane is Lane0.
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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_debug/rx_valid
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Date: February 2025
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Contact: Shradha Todi <shradha.t@samsung.com>
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Description: (RW) Write the lane number to be checked as valid or invalid.
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Read will return the status of PIPE RXVALID signal of the
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selected lane. The default selected lane is Lane0.
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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
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Date: February 2025
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Contact: Shradha Todi <shradha.t@samsung.com>
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Description: The "rasdes_err_inj" is a directory which can be used to inject
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errors into the system. The possible errors that can be injected
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are:
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1) tx_lcrc - TLP LCRC error injection TX Path
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2) b16_crc_dllp - 16b CRC error injection of ACK/NAK DLLP
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3) b16_crc_upd_fc - 16b CRC error injection of Update-FC DLLP
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4) tx_ecrc - TLP ECRC error injection TX Path
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5) fcrc_tlp - TLP's FCRC error injection TX Path
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6) parity_tsos - Parity error of TSOS
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7) parity_skpos - Parity error on SKPOS
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8) rx_lcrc - LCRC error injection RX Path
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9) rx_ecrc - ECRC error injection RX Path
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10) tlp_err_seq - TLPs SEQ# error
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11) ack_nak_dllp_seq - DLLPS ACK/NAK SEQ# error
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12) ack_nak_dllp - ACK/NAK DLLPs transmission block
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13) upd_fc_dllp - UpdateFC DLLPs transmission block
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14) nak_dllp - Always transmission for NAK DLLP
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15) inv_sync_hdr_sym - Invert SYNC header
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16) com_pad_ts1 - COM/PAD TS1 order set
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17) com_pad_ts2 - COM/PAD TS2 order set
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18) com_fts - COM/FTS FTS order set
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19) com_idl - COM/IDL E-idle order set
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20) end_edb - END/EDB symbol
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21) stp_sdp - STP/SDP symbol
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22) com_skp - COM/SKP SKP order set
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23) posted_tlp_hdr - Posted TLP Header credit value control
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24) non_post_tlp_hdr - Non-Posted TLP Header credit value control
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25) cmpl_tlp_hdr - Completion TLP Header credit value control
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26) posted_tlp_data - Posted TLP Data credit value control
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27) non_post_tlp_data - Non-Posted TLP Data credit value control
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28) cmpl_tlp_data - Completion TLP Data credit value control
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29) duplicate_tlp - Generates duplicate TLPs
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30) nullified_tlp - Generates Nullified TLPs
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(WO) Write to the attribute will prepare controller to inject
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the respective error in the next transmission of data.
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Parameter required to write will change in the following ways:
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- Errors 9 and 10 are sequence errors. The write command:
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echo <count> <diff> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
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<count>
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Number of errors to be injected
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<diff>
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The difference to add or subtract from natural
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sequence number to generate sequence error.
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Allowed range from -4095 to 4095
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- Errors 23 to 28 are credit value error insertions. The write
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command:
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echo <count> <diff> <vc> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
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<count>
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Number of errors to be injected
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<diff>
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The difference to add or subtract from UpdateFC
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credit value. Allowed range from -4095 to 4095
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<vc>
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Target VC number
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- All other errors. The write command:
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echo <count> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
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<count>
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Number of errors to be injected
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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/counter_enable
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Date: February 2025
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Contact: Shradha Todi <shradha.t@samsung.com>
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Description: The "rasdes_event_counters" is the directory which can be used
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to collect statistical data about the number of times a certain
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event has occurred in the controller. The list of possible
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events are:
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1) EBUF Overflow
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2) EBUF Underrun
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3) Decode Error
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4) Running Disparity Error
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5) SKP OS Parity Error
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6) SYNC Header Error
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7) Rx Valid De-assertion
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8) CTL SKP OS Parity Error
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9) 1st Retimer Parity Error
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10) 2nd Retimer Parity Error
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11) Margin CRC and Parity Error
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12) Detect EI Infer
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13) Receiver Error
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14) RX Recovery Req
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15) N_FTS Timeout
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16) Framing Error
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17) Deskew Error
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18) Framing Error In L0
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19) Deskew Uncompleted Error
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20) Bad TLP
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21) LCRC Error
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22) Bad DLLP
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23) Replay Number Rollover
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24) Replay Timeout
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25) Rx Nak DLLP
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26) Tx Nak DLLP
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27) Retry TLP
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28) FC Timeout
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29) Poisoned TLP
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30) ECRC Error
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31) Unsupported Request
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32) Completer Abort
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33) Completion Timeout
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34) EBUF SKP Add
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35) EBUF SKP Del
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(RW) Write 1 to enable the event counter and write 0 to disable
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the event counter. Read will return whether the counter is
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currently enabled or disabled. Counter is disabled by default.
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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/counter_value
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Date: February 2025
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Contact: Shradha Todi <shradha.t@samsung.com>
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Description: (RO) Read will return the current value of the event counter.
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To reset the counter, counter should be disabled first and then
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enabled back using the "counter_enable" attribute.
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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/lane_select
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Date: February 2025
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Contact: Shradha Todi <shradha.t@samsung.com>
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Description: (RW) Some lanes in the event list are lane specific events.
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These include events from 1 to 11, as well as, 34 and 35. Write
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the lane number for which you wish the counter to be enabled,
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disabled, or value dumped. Read will return the current
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selected lane number. Lane0 is selected by default.
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What: /sys/kernel/debug/dwc_pcie_<dev>/ltssm_status
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Date: February 2025
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Contact: Hans Zhang <18255117159@163.com>
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Description: (RO) Read will return the current PCIe LTSSM state in both
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string and raw value.
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