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PCI: dwc: Add debugfs property to provide LTSSM status of the PCIe link
Add the debugfs property to provide a view of the current link's LTSSM status from the Root Port device. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by: Niklas Cassel <cassel@kernel.org> Tested-by: Hrishikesh Deleep <hrishikesh.d@samsung.com> Link: https://lore.kernel.org/r/20250223141848.231232-1-18255117159@163.com [kwilczynski: commit log, refactor dw_ltssm_sts_string() to avoid compilation errors on platforms that do not set CONFIG_PCIE_DW_HOST] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
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3 changed files with 116 additions and 0 deletions
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@ -149,3 +149,9 @@ Description: (RW) Some lanes in the event list are lane specific events.
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the lane number for which you wish the counter to be enabled,
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disabled, or value dumped. Read will return the current
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selected lane number. Lane0 is selected by default.
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What: /sys/kernel/debug/dwc_pcie_<dev>/ltssm_status
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Date: February 2025
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Contact: Hans Zhang <18255117159@163.com>
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Description: (RO) Read will return the current PCIe LTSSM state in both
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string and raw value.
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@ -443,6 +443,72 @@ static ssize_t counter_value_read(struct file *file, char __user *buf,
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return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
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}
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static const char *ltssm_status_string(enum dw_pcie_ltssm ltssm)
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{
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const char *str;
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switch (ltssm) {
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#define DW_PCIE_LTSSM_NAME(n) case n: str = #n; break
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DETECT_QUIET);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DETECT_ACT);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_POLL_ACTIVE);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_POLL_COMPLIANCE);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_POLL_CONFIG);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_PRE_DETECT_QUIET);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DETECT_WAIT);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LINKWD_START);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LINKWD_ACEPT);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LANENUM_WAI);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_LANENUM_ACEPT);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_COMPLETE);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_CFG_IDLE);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_LOCK);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_SPEED);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_RCVRCFG);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_IDLE);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L0);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L0S);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L123_SEND_EIDLE);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L1_IDLE);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L2_IDLE);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L2_WAKE);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DISABLED_ENTRY);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DISABLED_IDLE);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_DISABLED);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_ENTRY);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_ACTIVE);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_EXIT);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_LPBK_EXIT_TIMEOUT);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_HOT_RESET_ENTRY);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_HOT_RESET);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ0);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ1);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ2);
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DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ3);
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default:
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str = "DW_PCIE_LTSSM_UNKNOWN";
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break;
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}
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return str + strlen("DW_PCIE_LTSSM_");
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}
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static int ltssm_status_show(struct seq_file *s, void *v)
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{
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struct dw_pcie *pci = s->private;
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enum dw_pcie_ltssm val;
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val = dw_pcie_get_ltssm(pci);
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seq_printf(s, "%s (0x%02x)\n", ltssm_status_string(val), val);
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return 0;
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}
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static int ltssm_status_open(struct inode *inode, struct file *file)
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{
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return single_open(file, ltssm_status_show, inode->i_private);
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}
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#define dwc_debugfs_create(name) \
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debugfs_create_file(#name, 0644, rasdes_debug, pci, \
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&dbg_ ## name ## _fops)
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@ -479,6 +545,11 @@ static const struct file_operations dwc_pcie_counter_value_ops = {
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.read = counter_value_read,
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};
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static const struct file_operations dwc_pcie_ltssm_status_ops = {
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.open = ltssm_status_open,
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.read = seq_read,
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};
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static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci)
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{
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struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
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@ -565,6 +636,12 @@ err_deinit:
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return ret;
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}
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static void dwc_pcie_ltssm_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
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{
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debugfs_create_file("ltssm_status", 0444, dir, pci,
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&dwc_pcie_ltssm_status_ops);
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}
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void dwc_pcie_debugfs_deinit(struct dw_pcie *pci)
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{
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if (!pci->debugfs)
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@ -595,4 +672,6 @@ void dwc_pcie_debugfs_init(struct dw_pcie *pci)
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if (err)
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dev_err(dev, "failed to initialize RAS DES debugfs, err=%d\n",
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err);
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dwc_pcie_ltssm_debugfs_init(pci, dir);
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}
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@ -330,9 +330,40 @@ enum dw_pcie_ltssm {
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/* Need to align with PCIE_PORT_DEBUG0 bits 0:5 */
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DW_PCIE_LTSSM_DETECT_QUIET = 0x0,
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DW_PCIE_LTSSM_DETECT_ACT = 0x1,
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DW_PCIE_LTSSM_POLL_ACTIVE = 0x2,
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DW_PCIE_LTSSM_POLL_COMPLIANCE = 0x3,
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DW_PCIE_LTSSM_POLL_CONFIG = 0x4,
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DW_PCIE_LTSSM_PRE_DETECT_QUIET = 0x5,
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DW_PCIE_LTSSM_DETECT_WAIT = 0x6,
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DW_PCIE_LTSSM_CFG_LINKWD_START = 0x7,
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DW_PCIE_LTSSM_CFG_LINKWD_ACEPT = 0x8,
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DW_PCIE_LTSSM_CFG_LANENUM_WAI = 0x9,
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DW_PCIE_LTSSM_CFG_LANENUM_ACEPT = 0xa,
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DW_PCIE_LTSSM_CFG_COMPLETE = 0xb,
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DW_PCIE_LTSSM_CFG_IDLE = 0xc,
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DW_PCIE_LTSSM_RCVRY_LOCK = 0xd,
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DW_PCIE_LTSSM_RCVRY_SPEED = 0xe,
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DW_PCIE_LTSSM_RCVRY_RCVRCFG = 0xf,
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DW_PCIE_LTSSM_RCVRY_IDLE = 0x10,
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DW_PCIE_LTSSM_L0 = 0x11,
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DW_PCIE_LTSSM_L0S = 0x12,
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DW_PCIE_LTSSM_L123_SEND_EIDLE = 0x13,
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DW_PCIE_LTSSM_L1_IDLE = 0x14,
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DW_PCIE_LTSSM_L2_IDLE = 0x15,
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DW_PCIE_LTSSM_L2_WAKE = 0x16,
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DW_PCIE_LTSSM_DISABLED_ENTRY = 0x17,
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DW_PCIE_LTSSM_DISABLED_IDLE = 0x18,
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DW_PCIE_LTSSM_DISABLED = 0x19,
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DW_PCIE_LTSSM_LPBK_ENTRY = 0x1a,
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DW_PCIE_LTSSM_LPBK_ACTIVE = 0x1b,
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DW_PCIE_LTSSM_LPBK_EXIT = 0x1c,
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DW_PCIE_LTSSM_LPBK_EXIT_TIMEOUT = 0x1d,
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DW_PCIE_LTSSM_HOT_RESET_ENTRY = 0x1e,
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DW_PCIE_LTSSM_HOT_RESET = 0x1f,
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DW_PCIE_LTSSM_RCVRY_EQ0 = 0x20,
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DW_PCIE_LTSSM_RCVRY_EQ1 = 0x21,
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DW_PCIE_LTSSM_RCVRY_EQ2 = 0x22,
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DW_PCIE_LTSSM_RCVRY_EQ3 = 0x23,
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DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF,
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};
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