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dt-bindings: pinctrl: qcom,apq8084-pinctrl: convert to dtschema
Convert the Qualcomm APQ8084 TLMM block bindings from text to yaml dt schema format. Signed-off-by: Rayyan Ansari <rayyan.ansari@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/20240709162009.5166-5-rayyan.ansari@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Rayyan Ansari
Linus Walleij
parent
06881e91f3
commit
d3f891f1d1
2 changed files with 129 additions and 188 deletions
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@ -1,188 +0,0 @@
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Qualcomm APQ8084 TLMM block
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This binding describes the Top Level Mode Multiplexer block found in the
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MSM8960 platform.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be "qcom,apq8084-pinctrl"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: the base address and size of the TLMM register space.
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- interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should specify the TLMM summary IRQ.
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- interrupt-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as an interrupt controller
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- #interrupt-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/interrupt-controller/irq.h>
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- gpio-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as a gpio controller
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- #gpio-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/gpio/gpio.h>
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- gpio-ranges:
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Usage: required
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Definition: see ../gpio/gpio.txt
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- gpio-reserved-ranges:
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Usage: optional
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Definition: see ../gpio/gpio.txt
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Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
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a general description of GPIO and interrupt bindings.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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PIN CONFIGURATION NODES:
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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- pins:
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Usage: required
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Value type: <string-array>
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Definition: List of gpio pins affected by the properties specified in
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this subnode. Valid pins are:
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gpio0-gpio146,
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sdc1_clk,
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sdc1_cmd,
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sdc1_data
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sdc2_clk,
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sdc2_cmd,
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sdc2_data
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- function:
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Usage: required
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Value type: <string>
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Definition: Specify the alternative function to be configured for the
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specified pins. Functions are only valid for gpio pins.
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Valid values are:
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adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
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blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
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blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
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blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
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blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
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blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3,
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blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8,
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blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
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blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
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blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
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blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2,
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cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
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cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
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edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i
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gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio,
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hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic,
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ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst,
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pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
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qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
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sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
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spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1,
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tsif2, uim, uim_batt_alarm
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- bias-disable:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as no pull.
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- bias-pull-down:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as pull down.
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- bias-pull-up:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as pull up.
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- output-high:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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high.
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Not valid for sdc pins.
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- output-low:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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low.
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Not valid for sdc pins.
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- drive-strength:
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Usage: optional
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Value type: <u32>
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Definition: Selects the drive strength for the specified pins, in mA.
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Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
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Example:
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tlmm: pinctrl@fd510000 {
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compatible = "qcom,apq8084-pinctrl";
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reg = <0xfd510000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 147>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 208 0>;
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uart2: uart2-default {
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mux {
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pins = "gpio4", "gpio5";
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function = "blsp_uart2";
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};
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tx {
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pins = "gpio4";
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drive-strength = <4>;
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bias-disable;
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};
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rx {
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pins = "gpio5";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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@ -0,0 +1,129 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,apq8084-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. APQ8084 TLMM block
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description: |
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Top Level Mode Multiplexer pin controller in Qualcomm APQ8084 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,apq8084-pinctrl
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-reserved-ranges: true
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-apq8084-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-apq8084-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-apq8084-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-6])$"
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- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
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sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
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blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
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blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
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blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3,
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blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,
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blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6,
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blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
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blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
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blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2,
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blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6,
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blsp_uart7, blsp_uart8, blsp_uart9, blsp_uart10,
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blsp_uart11, blsp_uart12, blsp_uim1, blsp_uim2,
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blsp_uim3, blsp_uim4, blsp_uim5, blsp_uim6, blsp_uim7,
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blsp_uim8, blsp_uim9, blsp_uim10, blsp_uim11,
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blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3,
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cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
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cci_timer0, cci_timer1, cci_timer2, cci_timer3,
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cci_timer4, edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3,
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gcc_obt, gcc_vtt, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2,
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gp0_clk, gp1_clk, gpio, hdmi_cec, hdmi_ddc, hdmi_dtest,
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hdmi_hpd, hdmi_rcv, hsic, ldo_en, ldo_update,
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mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst, pci_e1,
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pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
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qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
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sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
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spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s,
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tsif1, tsif2, uim, uim_batt_alarm ]
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required:
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- pins
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@fd510000 {
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compatible = "qcom,apq8084-pinctrl";
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reg = <0xfd510000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 147>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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uart-state {
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rx-pins {
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pins = "gpio5";
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function = "blsp_uart2";
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bias-pull-up;
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};
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tx-pins {
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pins = "gpio4";
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function = "blsp_uart2";
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bias-disable;
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};
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};
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};
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