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dt-bindings: pinctrl: qcom,ipq4019-pinctrl: convert to dtschema
Convert the Qualcomm IPQ4019 TLMM block bindings from text to yaml dt schema format. Signed-off-by: Rayyan Ansari <rayyan.ansari@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/20240709162009.5166-4-rayyan.ansari@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Rayyan Ansari
Linus Walleij
parent
df1acfd0a5
commit
06881e91f3
2 changed files with 102 additions and 85 deletions
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Qualcomm Atheros IPQ4019 TLMM block
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This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
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platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
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Required properties:
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- compatible: "qcom,ipq4019-pinctrl"
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- reg: Should be the base address and length of the TLMM block.
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- interrupts: Should be the parent IRQ of the TLMM block.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- #interrupt-cells: Should be two.
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- gpio-controller: Marks the device node as a GPIO controller.
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- #gpio-cells : Should be two.
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The first cell is the gpio pin number and the
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second cell is used for optional parameters.
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- gpio-ranges: see ../gpio/gpio.txt
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Optional properties:
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- gpio-reserved-ranges: see ../gpio/gpio.txt
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Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
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a general description of GPIO and interrupt bindings.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,
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drive-strength.
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Non-empty subnodes must specify the 'pins' property.
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Note that not all properties are valid for all pins.
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Valid values for qcom,pins are:
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gpio0-gpio99
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Supports mux, bias and drive-strength
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Valid values for qcom,function are:
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aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0,
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blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
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jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11,
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mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
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smart2, smart3, tm, wifi0, wifi1
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Example:
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq4019-pinctrl";
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reg = <0x1000000 0x300000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 100>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 208 0>;
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serial_pins: serial_pinmux {
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mux {
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pins = "gpio60", "gpio61";
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function = "blsp_uart0";
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bias-disable;
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};
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};
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};
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@ -0,0 +1,102 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,ipq4019-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. IPQ4019 TLMM block
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description: |
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Top Level Mode Multiplexer pin controller in Qualcomm IPQ4019 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,ipq4019-pinctrl
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-reserved-ranges: true
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-ipq4019-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-ipq4019-tlmm-state"
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additionalProperties: false
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"-hog(-[0-9]+)?$":
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required:
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- gpio-hog
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$defs:
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qcom-ipq4019-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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pattern: "^gpio([0-9]|[1-9][0-9])$"
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0,
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blsp_spi1, blsp_uart0, blsp_uart1, chip_rst, gpio,
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i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
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jtag, led0, led1, led2, led3, led4, led5, led6, led7,
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led8, led9, led10, led11, mdc, mdio, pcie, pmu,
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prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
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smart2, smart3, tm, wifi0, wifi1 ]
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required:
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- pins
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq4019-pinctrl";
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reg = <0x01000000 0x300000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 100>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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uart-state {
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pins = "gpio16", "gpio17";
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function = "blsp_uart0";
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bias-disable;
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};
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};
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