mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-09-18 22:14:16 +00:00
arm64: dts: qcom: sdm: change labels to lower-case
DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-16-0505bc7d2c56@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
Bjorn Andersson
parent
7b52cb2018
commit
4c047c473f
6 changed files with 291 additions and 291 deletions
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@ -49,170 +49,170 @@
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@100 {
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cpu0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&PERF_CPU_SLEEP_0
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&PERF_CPU_SLEEP_1
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&PERF_CLUSTER_SLEEP_0
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&PERF_CLUSTER_SLEEP_1
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&PERF_CLUSTER_SLEEP_2>;
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cpu-idle-states = <&perf_cpu_sleep_0
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&perf_cpu_sleep_1
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&perf_cluster_sleep_0
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&perf_cluster_sleep_1
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&perf_cluster_sleep_2>;
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capacity-dmips-mhz = <1126>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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next-level-cache = <&l2_1>;
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l2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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CPU1: cpu@101 {
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cpu1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x101>;
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enable-method = "psci";
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cpu-idle-states = <&PERF_CPU_SLEEP_0
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&PERF_CPU_SLEEP_1
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&PERF_CLUSTER_SLEEP_0
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&PERF_CLUSTER_SLEEP_1
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&PERF_CLUSTER_SLEEP_2>;
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cpu-idle-states = <&perf_cpu_sleep_0
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&perf_cpu_sleep_1
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&perf_cluster_sleep_0
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&perf_cluster_sleep_1
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&perf_cluster_sleep_2>;
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capacity-dmips-mhz = <1126>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_1>;
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next-level-cache = <&l2_1>;
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};
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CPU2: cpu@102 {
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cpu2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x102>;
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enable-method = "psci";
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cpu-idle-states = <&PERF_CPU_SLEEP_0
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&PERF_CPU_SLEEP_1
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&PERF_CLUSTER_SLEEP_0
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&PERF_CLUSTER_SLEEP_1
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&PERF_CLUSTER_SLEEP_2>;
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cpu-idle-states = <&perf_cpu_sleep_0
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&perf_cpu_sleep_1
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&perf_cluster_sleep_0
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&perf_cluster_sleep_1
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&perf_cluster_sleep_2>;
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capacity-dmips-mhz = <1126>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_1>;
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next-level-cache = <&l2_1>;
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};
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CPU3: cpu@103 {
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cpu3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x103>;
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enable-method = "psci";
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cpu-idle-states = <&PERF_CPU_SLEEP_0
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&PERF_CPU_SLEEP_1
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&PERF_CLUSTER_SLEEP_0
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&PERF_CLUSTER_SLEEP_1
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&PERF_CLUSTER_SLEEP_2>;
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cpu-idle-states = <&perf_cpu_sleep_0
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&perf_cpu_sleep_1
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&perf_cluster_sleep_0
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&perf_cluster_sleep_1
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&perf_cluster_sleep_2>;
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capacity-dmips-mhz = <1126>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_1>;
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next-level-cache = <&l2_1>;
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};
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CPU4: cpu@0 {
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cpu4: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&PWR_CPU_SLEEP_0
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&PWR_CPU_SLEEP_1
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&PWR_CLUSTER_SLEEP_0
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&PWR_CLUSTER_SLEEP_1
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&PWR_CLUSTER_SLEEP_2>;
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cpu-idle-states = <&pwr_cpu_sleep_0
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&pwr_cpu_sleep_1
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&pwr_cluster_sleep_0
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&pwr_cluster_sleep_1
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&pwr_cluster_sleep_2>;
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capacity-dmips-mhz = <1024>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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next-level-cache = <&l2_0>;
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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CPU5: cpu@1 {
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cpu5: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "psci";
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cpu-idle-states = <&PWR_CPU_SLEEP_0
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&PWR_CPU_SLEEP_1
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&PWR_CLUSTER_SLEEP_0
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&PWR_CLUSTER_SLEEP_1
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&PWR_CLUSTER_SLEEP_2>;
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cpu-idle-states = <&pwr_cpu_sleep_0
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&pwr_cpu_sleep_1
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&pwr_cluster_sleep_0
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&pwr_cluster_sleep_1
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&pwr_cluster_sleep_2>;
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capacity-dmips-mhz = <1024>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_0>;
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next-level-cache = <&l2_0>;
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};
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CPU6: cpu@2 {
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cpu6: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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enable-method = "psci";
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cpu-idle-states = <&PWR_CPU_SLEEP_0
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&PWR_CPU_SLEEP_1
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&PWR_CLUSTER_SLEEP_0
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&PWR_CLUSTER_SLEEP_1
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&PWR_CLUSTER_SLEEP_2>;
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cpu-idle-states = <&pwr_cpu_sleep_0
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&pwr_cpu_sleep_1
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&pwr_cluster_sleep_0
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&pwr_cluster_sleep_1
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&pwr_cluster_sleep_2>;
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capacity-dmips-mhz = <1024>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_0>;
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next-level-cache = <&l2_0>;
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};
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CPU7: cpu@3 {
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cpu7: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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enable-method = "psci";
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cpu-idle-states = <&PWR_CPU_SLEEP_0
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&PWR_CPU_SLEEP_1
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&PWR_CLUSTER_SLEEP_0
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&PWR_CLUSTER_SLEEP_1
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&PWR_CLUSTER_SLEEP_2>;
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cpu-idle-states = <&pwr_cpu_sleep_0
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&pwr_cpu_sleep_1
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&pwr_cluster_sleep_0
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&pwr_cluster_sleep_1
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&pwr_cluster_sleep_2>;
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capacity-dmips-mhz = <1024>;
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#cooling-cells = <2>;
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next-level-cache = <&L2_0>;
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next-level-cache = <&l2_0>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU4>;
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&CPU5>;
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&CPU6>;
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&CPU7>;
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cpu = <&cpu7>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU0>;
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&CPU1>;
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&CPU2>;
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&CPU3>;
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cpu = <&cpu3>;
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};
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};
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};
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@ -220,7 +220,7 @@
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idle-states {
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entry-method = "psci";
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PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
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pwr_cpu_sleep_0: cpu-sleep-0-0 {
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compatible = "arm,idle-state";
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idle-state-name = "pwr-retention";
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arm,psci-suspend-param = <0x40000002>;
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@ -229,7 +229,7 @@
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min-residency-us = <200>;
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};
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PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
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pwr_cpu_sleep_1: cpu-sleep-0-1 {
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compatible = "arm,idle-state";
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idle-state-name = "pwr-power-collapse";
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arm,psci-suspend-param = <0x40000003>;
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@ -239,7 +239,7 @@
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local-timer-stop;
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};
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PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
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perf_cpu_sleep_0: cpu-sleep-1-0 {
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compatible = "arm,idle-state";
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idle-state-name = "perf-retention";
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arm,psci-suspend-param = <0x40000002>;
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@ -248,7 +248,7 @@
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min-residency-us = <200>;
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};
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PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
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perf_cpu_sleep_1: cpu-sleep-1-1 {
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compatible = "arm,idle-state";
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idle-state-name = "perf-power-collapse";
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arm,psci-suspend-param = <0x40000003>;
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@ -258,7 +258,7 @@
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local-timer-stop;
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};
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PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
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pwr_cluster_sleep_0: cluster-sleep-0-0 {
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compatible = "arm,idle-state";
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idle-state-name = "pwr-cluster-dynamic-retention";
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arm,psci-suspend-param = <0x400000F2>;
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@ -268,7 +268,7 @@
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local-timer-stop;
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};
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PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
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pwr_cluster_sleep_1: cluster-sleep-0-1 {
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compatible = "arm,idle-state";
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idle-state-name = "pwr-cluster-retention";
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arm,psci-suspend-param = <0x400000F3>;
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@ -278,7 +278,7 @@
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local-timer-stop;
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};
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PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
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pwr_cluster_sleep_2: cluster-sleep-0-2 {
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compatible = "arm,idle-state";
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idle-state-name = "pwr-cluster-retention";
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arm,psci-suspend-param = <0x400000F4>;
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@ -288,7 +288,7 @@
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local-timer-stop;
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};
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PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
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perf_cluster_sleep_0: cluster-sleep-1-0 {
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compatible = "arm,idle-state";
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idle-state-name = "perf-cluster-dynamic-retention";
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arm,psci-suspend-param = <0x400000F2>;
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@ -298,7 +298,7 @@
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local-timer-stop;
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};
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PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
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perf_cluster_sleep_1: cluster-sleep-1-1 {
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compatible = "arm,idle-state";
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idle-state-name = "perf-cluster-retention";
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arm,psci-suspend-param = <0x400000F3>;
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@ -308,7 +308,7 @@
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local-timer-stop;
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};
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PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
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perf_cluster_sleep_2: cluster-sleep-1-2 {
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compatible = "arm,idle-state";
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idle-state-name = "perf-cluster-retention";
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arm,psci-suspend-param = <0x400000F4>;
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@ -85,49 +85,49 @@
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};
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};
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&CPU0 {
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&cpu0 {
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compatible = "qcom,kryo260";
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capacity-dmips-mhz = <1024>;
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/delete-property/ operating-points-v2;
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};
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&CPU1 {
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&cpu1 {
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compatible = "qcom,kryo260";
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capacity-dmips-mhz = <1024>;
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/delete-property/ operating-points-v2;
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};
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&CPU2 {
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&cpu2 {
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compatible = "qcom,kryo260";
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capacity-dmips-mhz = <1024>;
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/delete-property/ operating-points-v2;
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};
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&CPU3 {
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&cpu3 {
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compatible = "qcom,kryo260";
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capacity-dmips-mhz = <1024>;
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/delete-property/ operating-points-v2;
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};
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&CPU4 {
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&cpu4 {
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compatible = "qcom,kryo260";
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capacity-dmips-mhz = <640>;
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/delete-property/ operating-points-v2;
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};
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&CPU5 {
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&cpu5 {
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compatible = "qcom,kryo260";
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capacity-dmips-mhz = <640>;
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/delete-property/ operating-points-v2;
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};
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&CPU6 {
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&cpu6 {
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compatible = "qcom,kryo260";
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capacity-dmips-mhz = <640>;
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/delete-property/ operating-points-v2;
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};
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&CPU7 {
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&cpu7 {
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compatible = "qcom,kryo260";
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capacity-dmips-mhz = <640>;
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/delete-property/ operating-points-v2;
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|
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@ -32,7 +32,7 @@
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#address-cells = <2>;
|
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#size-cells = <0>;
|
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|
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CPU0: cpu@0 {
|
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cpu0: cpu@0 {
|
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device_type = "cpu";
|
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compatible = "qcom,kryo360";
|
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reg = <0x0 0x0>;
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|
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@ -43,15 +43,15 @@
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
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power-domains = <&CPU_PD0>;
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power-domains = <&cpu_pd0>;
|
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power-domain-names = "psci";
|
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next-level-cache = <&L2_0>;
|
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L2_0: l2-cache {
|
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next-level-cache = <&l2_0>;
|
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l2_0: l2-cache {
|
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compatible = "cache";
|
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next-level-cache = <&L3_0>;
|
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next-level-cache = <&l3_0>;
|
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cache-level = <2>;
|
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cache-unified;
|
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L3_0: l3-cache {
|
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l3_0: l3-cache {
|
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compatible = "cache";
|
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cache-level = <3>;
|
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cache-unified;
|
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|
|
@ -59,7 +59,7 @@
|
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};
|
||||
};
|
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|
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CPU1: cpu@100 {
|
||||
cpu1: cpu@100 {
|
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device_type = "cpu";
|
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compatible = "qcom,kryo360";
|
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reg = <0x0 0x100>;
|
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|
|
@ -70,18 +70,18 @@
|
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operating-points-v2 = <&cpu0_opp_table>;
|
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interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
|
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD1>;
|
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power-domains = <&cpu_pd1>;
|
||||
power-domain-names = "psci";
|
||||
next-level-cache = <&L2_100>;
|
||||
L2_100: l2-cache {
|
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next-level-cache = <&l2_100>;
|
||||
l2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
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cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU2: cpu@200 {
|
||||
cpu2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo360";
|
||||
reg = <0x0 0x200>;
|
||||
|
|
@ -92,18 +92,18 @@
|
|||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD2>;
|
||||
power-domains = <&cpu_pd2>;
|
||||
power-domain-names = "psci";
|
||||
next-level-cache = <&L2_200>;
|
||||
L2_200: l2-cache {
|
||||
next-level-cache = <&l2_200>;
|
||||
l2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@300 {
|
||||
cpu3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo360";
|
||||
reg = <0x0 0x300>;
|
||||
|
|
@ -114,18 +114,18 @@
|
|||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD3>;
|
||||
power-domains = <&cpu_pd3>;
|
||||
power-domain-names = "psci";
|
||||
next-level-cache = <&L2_300>;
|
||||
L2_300: l2-cache {
|
||||
next-level-cache = <&l2_300>;
|
||||
l2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU4: cpu@400 {
|
||||
cpu4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo360";
|
||||
reg = <0x0 0x400>;
|
||||
|
|
@ -136,18 +136,18 @@
|
|||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD4>;
|
||||
power-domains = <&cpu_pd4>;
|
||||
power-domain-names = "psci";
|
||||
next-level-cache = <&L2_400>;
|
||||
L2_400: l2-cache {
|
||||
next-level-cache = <&l2_400>;
|
||||
l2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU5: cpu@500 {
|
||||
cpu5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo360";
|
||||
reg = <0x0 0x500>;
|
||||
|
|
@ -158,18 +158,18 @@
|
|||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD5>;
|
||||
power-domains = <&cpu_pd5>;
|
||||
power-domain-names = "psci";
|
||||
next-level-cache = <&L2_500>;
|
||||
L2_500: l2-cache {
|
||||
next-level-cache = <&l2_500>;
|
||||
l2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU6: cpu@600 {
|
||||
cpu6: cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo360";
|
||||
reg = <0x0 0x600>;
|
||||
|
|
@ -180,18 +180,18 @@
|
|||
operating-points-v2 = <&cpu6_opp_table>;
|
||||
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD6>;
|
||||
power-domains = <&cpu_pd6>;
|
||||
power-domain-names = "psci";
|
||||
next-level-cache = <&L2_600>;
|
||||
L2_600: l2-cache {
|
||||
next-level-cache = <&l2_600>;
|
||||
l2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU7: cpu@700 {
|
||||
cpu7: cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo360";
|
||||
reg = <0x0 0x700>;
|
||||
|
|
@ -202,49 +202,49 @@
|
|||
operating-points-v2 = <&cpu6_opp_table>;
|
||||
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD7>;
|
||||
power-domains = <&cpu_pd7>;
|
||||
power-domain-names = "psci";
|
||||
next-level-cache = <&L2_700>;
|
||||
L2_700: l2-cache {
|
||||
next-level-cache = <&l2_700>;
|
||||
l2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
|
||||
core4 {
|
||||
cpu = <&CPU4>;
|
||||
cpu = <&cpu4>;
|
||||
};
|
||||
|
||||
core5 {
|
||||
cpu = <&CPU5>;
|
||||
cpu = <&cpu5>;
|
||||
};
|
||||
|
||||
core6 {
|
||||
cpu = <&CPU6>;
|
||||
cpu = <&cpu6>;
|
||||
};
|
||||
|
||||
core7 {
|
||||
cpu = <&CPU7>;
|
||||
cpu = <&cpu7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -252,7 +252,7 @@
|
|||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
|
||||
little_cpu_sleep_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "little-rail-power-collapse";
|
||||
arm,psci-suspend-param = <0x40000004>;
|
||||
|
|
@ -262,7 +262,7 @@
|
|||
local-timer-stop;
|
||||
};
|
||||
|
||||
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
|
||||
big_cpu_sleep_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "big-rail-power-collapse";
|
||||
arm,psci-suspend-param = <0x40000004>;
|
||||
|
|
@ -274,7 +274,7 @@
|
|||
};
|
||||
|
||||
domain-idle-states {
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
cluster_sleep_0: cluster-sleep-0 {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x4100c244>;
|
||||
entry-latency-us = <3263>;
|
||||
|
|
@ -429,57 +429,57 @@
|
|||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
|
||||
CPU_PD0: power-domain-cpu0 {
|
||||
cpu_pd0: power-domain-cpu0 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD1: power-domain-cpu1 {
|
||||
cpu_pd1: power-domain-cpu1 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD2: power-domain-cpu2 {
|
||||
cpu_pd2: power-domain-cpu2 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD3: power-domain-cpu3 {
|
||||
cpu_pd3: power-domain-cpu3 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD4: power-domain-cpu4 {
|
||||
cpu_pd4: power-domain-cpu4 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD5: power-domain-cpu5 {
|
||||
cpu_pd5: power-domain-cpu5 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD6: power-domain-cpu6 {
|
||||
cpu_pd6: power-domain-cpu6 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&big_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD7: power-domain-cpu7 {
|
||||
cpu_pd7: power-domain-cpu7 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&big_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CLUSTER_PD: power-domain-cluster {
|
||||
cluster_pd: power-domain-cluster {
|
||||
#power-domain-cells = <0>;
|
||||
domain-idle-states = <&CLUSTER_SLEEP_0>;
|
||||
domain-idle-states = <&cluster_sleep_0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1763,7 +1763,7 @@
|
|||
<SLEEP_TCS 3>,
|
||||
<WAKE_TCS 3>,
|
||||
<CONTROL_TCS 1>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
power-domains = <&cluster_pd>;
|
||||
|
||||
apps_bcm_voter: bcm-voter {
|
||||
compatible = "qcom,bcm-voter";
|
||||
|
|
|
|||
|
|
@ -164,7 +164,7 @@
|
|||
};
|
||||
|
||||
&cpu_idle_states {
|
||||
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
|
||||
little_cpu_sleep_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "little-power-down";
|
||||
arm,psci-suspend-param = <0x40000003>;
|
||||
|
|
@ -174,7 +174,7 @@
|
|||
local-timer-stop;
|
||||
};
|
||||
|
||||
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
|
||||
little_cpu_sleep_1: cpu-sleep-0-1 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "little-rail-power-down";
|
||||
arm,psci-suspend-param = <0x40000004>;
|
||||
|
|
@ -184,7 +184,7 @@
|
|||
local-timer-stop;
|
||||
};
|
||||
|
||||
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
|
||||
big_cpu_sleep_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "big-power-down";
|
||||
arm,psci-suspend-param = <0x40000003>;
|
||||
|
|
@ -194,7 +194,7 @@
|
|||
local-timer-stop;
|
||||
};
|
||||
|
||||
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
|
||||
big_cpu_sleep_1: cpu-sleep-1-1 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "big-rail-power-down";
|
||||
arm,psci-suspend-param = <0x40000004>;
|
||||
|
|
@ -204,7 +204,7 @@
|
|||
local-timer-stop;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
cluster_sleep_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "cluster-power-down";
|
||||
arm,psci-suspend-param = <0x400000F4>;
|
||||
|
|
@ -215,68 +215,68 @@
|
|||
};
|
||||
};
|
||||
|
||||
&CPU0 {
|
||||
&cpu0 {
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ power-domain-names;
|
||||
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
|
||||
&LITTLE_CPU_SLEEP_1
|
||||
&CLUSTER_SLEEP_0>;
|
||||
cpu-idle-states = <&little_cpu_sleep_0
|
||||
&little_cpu_sleep_1
|
||||
&cluster_sleep_0>;
|
||||
};
|
||||
|
||||
&CPU1 {
|
||||
&cpu1 {
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ power-domain-names;
|
||||
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
|
||||
&LITTLE_CPU_SLEEP_1
|
||||
&CLUSTER_SLEEP_0>;
|
||||
cpu-idle-states = <&little_cpu_sleep_0
|
||||
&little_cpu_sleep_1
|
||||
&cluster_sleep_0>;
|
||||
};
|
||||
|
||||
&CPU2 {
|
||||
&cpu2 {
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ power-domain-names;
|
||||
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
|
||||
&LITTLE_CPU_SLEEP_1
|
||||
&CLUSTER_SLEEP_0>;
|
||||
cpu-idle-states = <&little_cpu_sleep_0
|
||||
&little_cpu_sleep_1
|
||||
&cluster_sleep_0>;
|
||||
};
|
||||
|
||||
&CPU3 {
|
||||
&cpu3 {
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ power-domain-names;
|
||||
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
|
||||
&LITTLE_CPU_SLEEP_1
|
||||
&CLUSTER_SLEEP_0>;
|
||||
cpu-idle-states = <&little_cpu_sleep_0
|
||||
&little_cpu_sleep_1
|
||||
&cluster_sleep_0>;
|
||||
};
|
||||
|
||||
&CPU4 {
|
||||
&cpu4 {
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ power-domain-names;
|
||||
cpu-idle-states = <&BIG_CPU_SLEEP_0
|
||||
&BIG_CPU_SLEEP_1
|
||||
&CLUSTER_SLEEP_0>;
|
||||
cpu-idle-states = <&big_cpu_sleep_0
|
||||
&big_cpu_sleep_1
|
||||
&cluster_sleep_0>;
|
||||
};
|
||||
|
||||
&CPU5 {
|
||||
&cpu5 {
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ power-domain-names;
|
||||
cpu-idle-states = <&BIG_CPU_SLEEP_0
|
||||
&BIG_CPU_SLEEP_1
|
||||
&CLUSTER_SLEEP_0>;
|
||||
cpu-idle-states = <&big_cpu_sleep_0
|
||||
&big_cpu_sleep_1
|
||||
&cluster_sleep_0>;
|
||||
};
|
||||
|
||||
&CPU6 {
|
||||
&cpu6 {
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ power-domain-names;
|
||||
cpu-idle-states = <&BIG_CPU_SLEEP_0
|
||||
&BIG_CPU_SLEEP_1
|
||||
&CLUSTER_SLEEP_0>;
|
||||
cpu-idle-states = <&big_cpu_sleep_0
|
||||
&big_cpu_sleep_1
|
||||
&cluster_sleep_0>;
|
||||
};
|
||||
|
||||
&CPU7 {
|
||||
&cpu7 {
|
||||
/delete-property/ power-domains;
|
||||
/delete-property/ power-domain-names;
|
||||
cpu-idle-states = <&BIG_CPU_SLEEP_0
|
||||
&BIG_CPU_SLEEP_1
|
||||
&CLUSTER_SLEEP_0>;
|
||||
cpu-idle-states = <&big_cpu_sleep_0
|
||||
&big_cpu_sleep_1
|
||||
&cluster_sleep_0>;
|
||||
};
|
||||
|
||||
&lmh_cluster0 {
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
};
|
||||
|
||||
/* Fixed crystal oscillator dedicated to MCP2517FD */
|
||||
clk40M: can-clock {
|
||||
clk40m: can-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <40000000>;
|
||||
|
|
@ -863,7 +863,7 @@
|
|||
can@0 {
|
||||
compatible = "microchip,mcp2517fd";
|
||||
reg = <0>;
|
||||
clocks = <&clk40M>;
|
||||
clocks = <&clk40m>;
|
||||
interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
|
||||
spi-max-frequency = <10000000>;
|
||||
vdd-supply = <&vdc_5v>;
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x0>;
|
||||
|
|
@ -103,16 +103,16 @@
|
|||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
power-domains = <&cpu_pd0>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
next-level-cache = <&l2_0>;
|
||||
l2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
L3_0: l3-cache {
|
||||
next-level-cache = <&l3_0>;
|
||||
l3_0: l3-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
|
|
@ -120,7 +120,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
cpu1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x100>;
|
||||
|
|
@ -132,19 +132,19 @@
|
|||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD1>;
|
||||
power-domains = <&cpu_pd1>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_100>;
|
||||
L2_100: l2-cache {
|
||||
next-level-cache = <&l2_100>;
|
||||
l2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU2: cpu@200 {
|
||||
cpu2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x200>;
|
||||
|
|
@ -156,19 +156,19 @@
|
|||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD2>;
|
||||
power-domains = <&cpu_pd2>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_200>;
|
||||
L2_200: l2-cache {
|
||||
next-level-cache = <&l2_200>;
|
||||
l2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@300 {
|
||||
cpu3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x300>;
|
||||
|
|
@ -181,18 +181,18 @@
|
|||
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
power-domains = <&CPU_PD3>;
|
||||
power-domains = <&cpu_pd3>;
|
||||
power-domain-names = "psci";
|
||||
next-level-cache = <&L2_300>;
|
||||
L2_300: l2-cache {
|
||||
next-level-cache = <&l2_300>;
|
||||
l2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU4: cpu@400 {
|
||||
cpu4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x400>;
|
||||
|
|
@ -204,19 +204,19 @@
|
|||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD4>;
|
||||
power-domains = <&cpu_pd4>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_400>;
|
||||
L2_400: l2-cache {
|
||||
next-level-cache = <&l2_400>;
|
||||
l2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU5: cpu@500 {
|
||||
cpu5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x500>;
|
||||
|
|
@ -228,19 +228,19 @@
|
|||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD5>;
|
||||
power-domains = <&cpu_pd5>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_500>;
|
||||
L2_500: l2-cache {
|
||||
next-level-cache = <&l2_500>;
|
||||
l2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU6: cpu@600 {
|
||||
cpu6: cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x600>;
|
||||
|
|
@ -252,19 +252,19 @@
|
|||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD6>;
|
||||
power-domains = <&cpu_pd6>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_600>;
|
||||
L2_600: l2-cache {
|
||||
next-level-cache = <&l2_600>;
|
||||
l2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU7: cpu@700 {
|
||||
cpu7: cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x700>;
|
||||
|
|
@ -276,50 +276,50 @@
|
|||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
|
||||
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
|
||||
power-domains = <&CPU_PD7>;
|
||||
power-domains = <&cpu_pd7>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_700>;
|
||||
L2_700: l2-cache {
|
||||
next-level-cache = <&l2_700>;
|
||||
l2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
|
||||
core4 {
|
||||
cpu = <&CPU4>;
|
||||
cpu = <&cpu4>;
|
||||
};
|
||||
|
||||
core5 {
|
||||
cpu = <&CPU5>;
|
||||
cpu = <&cpu5>;
|
||||
};
|
||||
|
||||
core6 {
|
||||
cpu = <&CPU6>;
|
||||
cpu = <&cpu6>;
|
||||
};
|
||||
|
||||
core7 {
|
||||
cpu = <&CPU7>;
|
||||
cpu = <&cpu7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -327,7 +327,7 @@
|
|||
cpu_idle_states: idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
|
||||
little_cpu_sleep_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "little-rail-power-collapse";
|
||||
arm,psci-suspend-param = <0x40000004>;
|
||||
|
|
@ -337,7 +337,7 @@
|
|||
local-timer-stop;
|
||||
};
|
||||
|
||||
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
|
||||
big_cpu_sleep_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "big-rail-power-collapse";
|
||||
arm,psci-suspend-param = <0x40000004>;
|
||||
|
|
@ -349,7 +349,7 @@
|
|||
};
|
||||
|
||||
domain-idle-states {
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
cluster_sleep_0: cluster-sleep-0 {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x4100c244>;
|
||||
entry-latency-us = <3263>;
|
||||
|
|
@ -717,57 +717,57 @@
|
|||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
|
||||
CPU_PD0: power-domain-cpu0 {
|
||||
cpu_pd0: power-domain-cpu0 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD1: power-domain-cpu1 {
|
||||
cpu_pd1: power-domain-cpu1 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD2: power-domain-cpu2 {
|
||||
cpu_pd2: power-domain-cpu2 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD3: power-domain-cpu3 {
|
||||
cpu_pd3: power-domain-cpu3 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD4: power-domain-cpu4 {
|
||||
cpu_pd4: power-domain-cpu4 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&big_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD5: power-domain-cpu5 {
|
||||
cpu_pd5: power-domain-cpu5 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&big_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD6: power-domain-cpu6 {
|
||||
cpu_pd6: power-domain-cpu6 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&big_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD7: power-domain-cpu7 {
|
||||
cpu_pd7: power-domain-cpu7 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&big_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CLUSTER_PD: power-domain-cluster {
|
||||
cluster_pd: power-domain-cluster {
|
||||
#power-domain-cells = <0>;
|
||||
domain-idle-states = <&CLUSTER_SLEEP_0>;
|
||||
domain-idle-states = <&cluster_sleep_0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -3615,7 +3615,7 @@
|
|||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07040000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU0>;
|
||||
cpu = <&cpu0>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
|
@ -3635,7 +3635,7 @@
|
|||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07140000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU1>;
|
||||
cpu = <&cpu1>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
|
@ -3655,7 +3655,7 @@
|
|||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07240000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU2>;
|
||||
cpu = <&cpu2>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
|
@ -3675,7 +3675,7 @@
|
|||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07340000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU3>;
|
||||
cpu = <&cpu3>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
|
@ -3695,7 +3695,7 @@
|
|||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07440000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU4>;
|
||||
cpu = <&cpu4>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
|
@ -3715,7 +3715,7 @@
|
|||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07540000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU5>;
|
||||
cpu = <&cpu5>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
|
@ -3735,7 +3735,7 @@
|
|||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07640000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU6>;
|
||||
cpu = <&cpu6>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
|
@ -3755,7 +3755,7 @@
|
|||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07740000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU7>;
|
||||
cpu = <&cpu7>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
|
@ -3959,7 +3959,7 @@
|
|||
compatible = "qcom,sdm845-lmh";
|
||||
reg = <0 0x17d70800 0 0x400>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cpus = <&CPU4>;
|
||||
cpus = <&cpu4>;
|
||||
qcom,lmh-temp-arm-millicelsius = <65000>;
|
||||
qcom,lmh-temp-low-millicelsius = <94500>;
|
||||
qcom,lmh-temp-high-millicelsius = <95000>;
|
||||
|
|
@ -3971,7 +3971,7 @@
|
|||
compatible = "qcom,sdm845-lmh";
|
||||
reg = <0 0x17d78800 0 0x400>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cpus = <&CPU0>;
|
||||
cpus = <&cpu0>;
|
||||
qcom,lmh-temp-arm-millicelsius = <65000>;
|
||||
qcom,lmh-temp-low-millicelsius = <94500>;
|
||||
qcom,lmh-temp-high-millicelsius = <95000>;
|
||||
|
|
@ -5278,7 +5278,7 @@
|
|||
<SLEEP_TCS 3>,
|
||||
<WAKE_TCS 3>,
|
||||
<CONTROL_TCS 1>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
power-domains = <&cluster_pd>;
|
||||
|
||||
apps_bcm_voter: bcm-voter {
|
||||
compatible = "qcom,bcm-voter";
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue