mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-09-18 22:14:16 +00:00
arm64: dts: qcom: sm: change labels to lower-case
DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-15-0505bc7d2c56@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
Bjorn Andersson
parent
20eb2057b3
commit
7b52cb2018
4 changed files with 188 additions and 188 deletions
|
|
@ -25,7 +25,7 @@
|
|||
};
|
||||
|
||||
clocks {
|
||||
clk40M: can-clk {
|
||||
clk40m: can-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <40000000>;
|
||||
#clock-cells = <0>;
|
||||
|
|
@ -537,7 +537,7 @@
|
|||
compatible = "microchip,mcp2518fd";
|
||||
reg = <0>;
|
||||
interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk40M>;
|
||||
clocks = <&clk40m>;
|
||||
spi-max-frequency = <10000000>;
|
||||
vdd-supply = <&vdc_5v>;
|
||||
xceiver-supply = <&vdc_5v>;
|
||||
|
|
|
|||
|
|
@ -46,25 +46,25 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x0>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
next-level-cache = <&l2_0>;
|
||||
power-domains = <&cpu_pd0>;
|
||||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
L2_0: l2-cache {
|
||||
l2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
|
||||
L3_0: l3-cache {
|
||||
l3_0: l3-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
|
|
@ -72,178 +72,178 @@
|
|||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
cpu1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x100>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_100>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
next-level-cache = <&l2_100>;
|
||||
power-domains = <&cpu_pd0>;
|
||||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
L2_100: l2-cache {
|
||||
l2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU2: cpu@200 {
|
||||
cpu2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x200>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_200>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
next-level-cache = <&l2_200>;
|
||||
power-domains = <&cpu_pd0>;
|
||||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
L2_200: l2-cache {
|
||||
l2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@300 {
|
||||
cpu3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x300>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_300>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
next-level-cache = <&l2_300>;
|
||||
power-domains = <&cpu_pd0>;
|
||||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
L2_300: l2-cache {
|
||||
l2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU4: cpu@400 {
|
||||
cpu4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x400>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_400>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
next-level-cache = <&l2_400>;
|
||||
power-domains = <&cpu_pd0>;
|
||||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
L2_400: l2-cache {
|
||||
l2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU5: cpu@500 {
|
||||
cpu5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x500>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_500>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
next-level-cache = <&l2_500>;
|
||||
power-domains = <&cpu_pd0>;
|
||||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
L2_500: l2-cache {
|
||||
l2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU6: cpu@600 {
|
||||
cpu6: cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a78";
|
||||
reg = <0x0 0x600>;
|
||||
clocks = <&cpufreq_hw 1>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_600>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
next-level-cache = <&l2_600>;
|
||||
power-domains = <&cpu_pd0>;
|
||||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
L2_600: l2-cache {
|
||||
l2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU7: cpu@700 {
|
||||
cpu7: cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a78";
|
||||
reg = <0x0 0x700>;
|
||||
clocks = <&cpufreq_hw 1>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_700>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
next-level-cache = <&l2_700>;
|
||||
power-domains = <&cpu_pd0>;
|
||||
power-domain-names = "psci";
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
L2_700: l2-cache {
|
||||
l2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
|
||||
core4 {
|
||||
cpu = <&CPU4>;
|
||||
cpu = <&cpu4>;
|
||||
};
|
||||
|
||||
core5 {
|
||||
cpu = <&CPU5>;
|
||||
cpu = <&cpu5>;
|
||||
};
|
||||
|
||||
core6 {
|
||||
cpu = <&CPU6>;
|
||||
cpu = <&cpu6>;
|
||||
};
|
||||
|
||||
core7 {
|
||||
cpu = <&CPU7>;
|
||||
cpu = <&cpu7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -251,7 +251,7 @@
|
|||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
|
||||
little_cpu_sleep_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x40000004>;
|
||||
entry-latency-us = <800>;
|
||||
|
|
@ -260,7 +260,7 @@
|
|||
local-timer-stop;
|
||||
};
|
||||
|
||||
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
|
||||
big_cpu_sleep_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x40000004>;
|
||||
entry-latency-us = <600>;
|
||||
|
|
@ -271,7 +271,7 @@
|
|||
};
|
||||
|
||||
domain-idle-states {
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
cluster_sleep_0: cluster-sleep-0 {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x41000044>;
|
||||
entry-latency-us = <1050>;
|
||||
|
|
@ -279,7 +279,7 @@
|
|||
min-residency-us = <5309>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_1: cluster-sleep-1 {
|
||||
cluster_sleep_1: cluster-sleep-1 {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x41003344>;
|
||||
entry-latency-us = <1561>;
|
||||
|
|
@ -309,57 +309,57 @@
|
|||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
|
||||
CPU_PD0: power-domain-cpu0 {
|
||||
cpu_pd0: power-domain-cpu0 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD1: power-domain-cpu1 {
|
||||
cpu_pd1: power-domain-cpu1 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD2: power-domain-cpu2 {
|
||||
cpu_pd2: power-domain-cpu2 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD3: power-domain-cpu3 {
|
||||
cpu_pd3: power-domain-cpu3 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD4: power-domain-cpu4 {
|
||||
cpu_pd4: power-domain-cpu4 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&big_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD5: power-domain-cpu5 {
|
||||
cpu_pd5: power-domain-cpu5 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&big_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD6: power-domain-cpu6 {
|
||||
cpu_pd6: power-domain-cpu6 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&big_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CPU_PD7: power-domain-cpu7 {
|
||||
cpu_pd7: power-domain-cpu7 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&big_cpu_sleep_0>;
|
||||
};
|
||||
|
||||
CLUSTER_PD: power-domain-cpu-cluster0 {
|
||||
cluster_pd: power-domain-cpu-cluster0 {
|
||||
#power-domain-cells = <0>;
|
||||
domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
|
||||
domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -579,7 +579,7 @@
|
|||
qcom,drv-id = <2>;
|
||||
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
|
||||
<WAKE_TCS 3>, <CONTROL_TCS 0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
power-domains = <&cluster_pd>;
|
||||
|
||||
apps_bcm_voter: bcm-voter {
|
||||
compatible = "qcom,bcm-voter";
|
||||
|
|
|
|||
|
|
@ -37,122 +37,122 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo260";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
next-level-cache = <&l2_0>;
|
||||
l2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo260";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
next-level-cache = <&L2_0>;
|
||||
next-level-cache = <&l2_0>;
|
||||
};
|
||||
|
||||
CPU2: cpu@2 {
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo260";
|
||||
reg = <0x0 0x2>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
next-level-cache = <&L2_0>;
|
||||
next-level-cache = <&l2_0>;
|
||||
};
|
||||
|
||||
CPU3: cpu@3 {
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo260";
|
||||
reg = <0x0 0x3>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
next-level-cache = <&L2_0>;
|
||||
next-level-cache = <&l2_0>;
|
||||
};
|
||||
|
||||
CPU4: cpu@100 {
|
||||
cpu4: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo260";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1638>;
|
||||
next-level-cache = <&L2_1>;
|
||||
L2_1: l2-cache {
|
||||
next-level-cache = <&l2_1>;
|
||||
l2_1: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
|
||||
CPU5: cpu@101 {
|
||||
cpu5: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo260";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1638>;
|
||||
next-level-cache = <&L2_1>;
|
||||
next-level-cache = <&l2_1>;
|
||||
};
|
||||
|
||||
CPU6: cpu@102 {
|
||||
cpu6: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo260";
|
||||
reg = <0x0 0x102>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1638>;
|
||||
next-level-cache = <&L2_1>;
|
||||
next-level-cache = <&l2_1>;
|
||||
};
|
||||
|
||||
CPU7: cpu@103 {
|
||||
cpu7: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo260";
|
||||
reg = <0x0 0x103>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1638>;
|
||||
next-level-cache = <&L2_1>;
|
||||
next-level-cache = <&l2_1>;
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU4>;
|
||||
cpu = <&cpu4>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU5>;
|
||||
cpu = <&cpu5>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU6>;
|
||||
cpu = <&cpu6>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU7>;
|
||||
cpu = <&cpu7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -38,25 +38,25 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo660";
|
||||
reg = <0x0 0x0>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
next-level-cache = <&l2_0>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
|
||||
power-domains = <&CPU_PD0>;
|
||||
power-domains = <&cpu_pd0>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_0: l2-cache {
|
||||
l2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
L3_0: l3-cache {
|
||||
next-level-cache = <&l3_0>;
|
||||
l3_0: l3-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
|
|
@ -64,185 +64,185 @@
|
|||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
cpu1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo660";
|
||||
reg = <0x0 0x100>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_100>;
|
||||
next-level-cache = <&l2_100>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
|
||||
power-domains = <&CPU_PD1>;
|
||||
power-domains = <&cpu_pd1>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_100: l2-cache {
|
||||
l2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU2: cpu@200 {
|
||||
cpu2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo660";
|
||||
reg = <0x0 0x200>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_200>;
|
||||
next-level-cache = <&l2_200>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
|
||||
power-domains = <&CPU_PD2>;
|
||||
power-domains = <&cpu_pd2>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_200: l2-cache {
|
||||
l2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@300 {
|
||||
cpu3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo660";
|
||||
reg = <0x0 0x300>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_300>;
|
||||
next-level-cache = <&l2_300>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
|
||||
power-domains = <&CPU_PD3>;
|
||||
power-domains = <&cpu_pd3>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_300: l2-cache {
|
||||
l2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU4: cpu@400 {
|
||||
cpu4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo660";
|
||||
reg = <0x0 0x400>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_400>;
|
||||
next-level-cache = <&l2_400>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
|
||||
power-domains = <&CPU_PD4>;
|
||||
power-domains = <&cpu_pd4>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_400: l2-cache {
|
||||
l2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU5: cpu@500 {
|
||||
cpu5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo660";
|
||||
reg = <0x0 0x500>;
|
||||
clocks = <&cpufreq_hw 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_500>;
|
||||
next-level-cache = <&l2_500>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
|
||||
power-domains = <&CPU_PD5>;
|
||||
power-domains = <&cpu_pd5>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_500: l2-cache {
|
||||
l2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU6: cpu@600 {
|
||||
cpu6: cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo660";
|
||||
reg = <0x0 0x600>;
|
||||
clocks = <&cpufreq_hw 1>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_600>;
|
||||
next-level-cache = <&l2_600>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu6_opp_table>;
|
||||
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
|
||||
power-domains = <&CPU_PD6>;
|
||||
power-domains = <&cpu_pd6>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_600: l2-cache {
|
||||
l2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU7: cpu@700 {
|
||||
cpu7: cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo660";
|
||||
reg = <0x0 0x700>;
|
||||
clocks = <&cpufreq_hw 1>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_700>;
|
||||
next-level-cache = <&l2_700>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu6_opp_table>;
|
||||
interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>;
|
||||
power-domains = <&CPU_PD7>;
|
||||
power-domains = <&cpu_pd7>;
|
||||
power-domain-names = "psci";
|
||||
#cooling-cells = <2>;
|
||||
L2_700: l2-cache {
|
||||
l2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3_0>;
|
||||
next-level-cache = <&l3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
|
||||
core4 {
|
||||
cpu = <&CPU4>;
|
||||
cpu = <&cpu4>;
|
||||
};
|
||||
|
||||
core5 {
|
||||
cpu = <&CPU5>;
|
||||
cpu = <&cpu5>;
|
||||
};
|
||||
|
||||
core6 {
|
||||
cpu = <&CPU6>;
|
||||
cpu = <&cpu6>;
|
||||
};
|
||||
|
||||
core7 {
|
||||
cpu = <&CPU7>;
|
||||
cpu = <&cpu7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -250,7 +250,7 @@
|
|||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
|
||||
little_cpu_sleep_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "silver-power-collapse";
|
||||
arm,psci-suspend-param = <0x40000003>;
|
||||
|
|
@ -260,7 +260,7 @@
|
|||
local-timer-stop;
|
||||
};
|
||||
|
||||
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
|
||||
little_cpu_sleep_1: cpu-sleep-0-1 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "silver-rail-power-collapse";
|
||||
arm,psci-suspend-param = <0x40000004>;
|
||||
|
|
@ -270,7 +270,7 @@
|
|||
local-timer-stop;
|
||||
};
|
||||
|
||||
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
|
||||
big_cpu_sleep_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "gold-power-collapse";
|
||||
arm,psci-suspend-param = <0x40000003>;
|
||||
|
|
@ -280,7 +280,7 @@
|
|||
local-timer-stop;
|
||||
};
|
||||
|
||||
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
|
||||
big_cpu_sleep_1: cpu-sleep-1-1 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "gold-rail-power-collapse";
|
||||
arm,psci-suspend-param = <0x40000004>;
|
||||
|
|
@ -292,7 +292,7 @@
|
|||
};
|
||||
|
||||
domain-idle-states {
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
cluster_sleep_0: cluster-sleep-0 {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x41000044>;
|
||||
entry-latency-us = <2752>;
|
||||
|
|
@ -455,58 +455,58 @@
|
|||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
|
||||
CPU_PD0: power-domain-cpu0 {
|
||||
cpu_pd0: power-domain-cpu0 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
|
||||
};
|
||||
|
||||
CPU_PD1: power-domain-cpu1 {
|
||||
cpu_pd1: power-domain-cpu1 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
|
||||
};
|
||||
|
||||
CPU_PD2: power-domain-cpu2 {
|
||||
cpu_pd2: power-domain-cpu2 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
|
||||
};
|
||||
|
||||
CPU_PD3: power-domain-cpu3 {
|
||||
cpu_pd3: power-domain-cpu3 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
|
||||
};
|
||||
|
||||
CPU_PD4: power-domain-cpu4 {
|
||||
cpu_pd4: power-domain-cpu4 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
|
||||
};
|
||||
|
||||
CPU_PD5: power-domain-cpu5 {
|
||||
cpu_pd5: power-domain-cpu5 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
|
||||
};
|
||||
|
||||
CPU_PD6: power-domain-cpu6 {
|
||||
cpu_pd6: power-domain-cpu6 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
|
||||
};
|
||||
|
||||
CPU_PD7: power-domain-cpu7 {
|
||||
cpu_pd7: power-domain-cpu7 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
|
||||
power-domains = <&cluster_pd>;
|
||||
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
|
||||
};
|
||||
|
||||
CLUSTER_PD: power-domain-cpu-cluster0 {
|
||||
cluster_pd: power-domain-cpu-cluster0 {
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&mpm>;
|
||||
domain-idle-states = <&CLUSTER_SLEEP_0>;
|
||||
domain-idle-states = <&cluster_sleep_0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue