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riscv: dts: spacemit: add reset support for the K1 SoC

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Define syscon nodes for the RCPU, RCPU2, and APBC2 SpacemiT CCUS, which
currently support resets but not clocks in the SpacemiT K1.

Signed-off-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250702113709.291748-7-elder@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
This commit is contained in:
Alex Elder 2025-07-02 06:37:08 -05:00 • committed by Yixun Lan
parent aadc509afc
commit 2c0cf4fed0
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GPG key ID: 31AAEA47594DBBED
1 changed files with 18 additions and 0 deletions
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18
arch/riscv/boot/dts/spacemit/k1.dtsi
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@ -346,6 +346,18 @@
dma-noncoherent;
ranges;
syscon_rcpu: system-controller@c0880000 {
compatible = "spacemit,k1-syscon-rcpu";
reg = <0x0 0xc0880000 0x0 0x2048>;
#reset-cells = <1>;
};
syscon_rcpu2: system-controller@c0888000 {
compatible = "spacemit,k1-syscon-rcpu2";
reg = <0x0 0xc0888000 0x0 0x28>;
#reset-cells = <1>;
};
syscon_apbc: system-controller@d4015000 {
compatible = "spacemit,k1-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
@ -562,6 +574,12 @@
<&cpu7_intc 3>, <&cpu7_intc 7>;
};
syscon_apbc2: system-controller@f0610000 {
compatible = "spacemit,k1-syscon-apbc2";
reg = <0x0 0xf0610000 0x0 0x20>;
#reset-cells = <1>;
};
sec_uart1: serial@f0612000 {
compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xf0612000 0x0 0x100>;