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RISC-V SpacemiT Binding for 6.17
- Reset DT Binding for K1 SoC -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQKTBAABCgB9FiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmhmkUdfFIAAAAAALgAo aXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5maWZ0aGhvcnNlbWFuLm5ldEI1 QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRUQACgkQMarqR1lN u+2Phw/+MW1m6c7LmOAelyT1F8OikT7AHqfc9spu38Yj3yYR1wshlayzzJIaBE6J SI0dZ6MiqqMV5p5kYmh99M8K3rpqZxbHNPyIdzpoSBEV84zZCODUFGzW4igVupmK lGkk/trNf4sDzZZE0Kd4TkNvVNXamXMEcATbLMEpMFBY5sQKCPW5v4IlzsewARcF D5MuP7uCZlufRZ3fIuTMktstUdmnI9H6I34TYFa3CB3jHf2aSffeN6rDGH4ks2NQ A+pCkeZLD00sxd40bmoWccrGdxhzZCBKw1sdQ1uJR2D5rXLmg6CcwSRbfoiazAkA n6shnjOS0vOv5ZVEKJyFc1Fv7QK1kYpRiAbpPMm4gmPxBbqJdpzDUwNhipL+jcKV m/wryInuL0sfev2Sp4mMXbnudCurD0Ssr498l/SkBr3QrWJ+3UXUspXhCYp7pMcz EulAVJpvktcE8wcY5b2J+tAIShYtL1merzsyOu05sf+PWYSrOCpDgh3dQITxwqKG UdSxYkDExoo5CodSliCn9yn2E6E+GpKOTbb9QGcwZOf6skwCnLiRWfR5p/SHHevf FP9uJbk788THprkSb4VGxSQ9+EEmzoiRVWS+ke1blVQUdTJya59CXc+axKzPVYAZ +XK/Wikty24eR39meGp9T27n2ICj3OBrWGxB5wmFaevt4CdVOrg= =d168 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQKTBAABCgB9FiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmhnImhfFIAAAAAALgAo aXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5maWZ0aGhvcnNlbWFuLm5ldEI1 QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRUQACgkQMarqR1lN u+0fPg//fPSRInWvCmyChC1yYW93DPFW6SolgnLXR8VaDzy04GFqVjTvmC7FBm8b QmUIdGfV3ngfqDiMw4Tm1VZt3Hma45kcXvjv/U3aG04eYQ+Mx2bwfnqbtQxSZ0kb fJWD/GCEwz21fuX+fY2xPcixNyVT/+wM7pME9cf0ALyaPAFgxHgbIRNilUoISaoP UkXmkIjKvbsgOL3DOLCXMYctH+8W69IOaTtVKVl1Pos/+nvSv2Xj8AKUfkpGTdug 3QPJqt1pZa5OIVZ/k6s56JOvZlzv/zozXF2KhcAZ4MzP/JObhpI1zOFD7he9xeGq 8IL9zi6bAKj1TcOPUAfolDuSjAXJp9h96EbYMvbs1EavTT5x6tVIEYK9kAVf0o+m xrfXwPLnP5VxIMM2fEtyFS1qBQwFnhhW/t2w1iiI8PmTZ0ndHUicL5YAW7PyrMQM MEF3H/xwyfv8O+t2iP/kkp4sDXqmDsBcuVeLXSuiyJJ6/YhELimK7MJhZE0rAaxl Uby/4gL7vMUS4M7Bjl1dd7CD3btn+u2JihRtCVkNTaAqnUOTci9sgqXK9F4KfLVR mluTx2J/lHxZWe2ZRJpGbR4Tu0lkb8si6k9aK8yAmiltlLaoNd4FFTPOi73traaR Pp+Iirmz/f8m7Rx9dUI77MnXwAelVBfShxlVdEYFn3+7Ki2h6iw= =EytQ -----END PGP SIGNATURE----- Merge tag 'spacemit-reset-binding-for-6.17-1' of https://github.com/spacemit-com/linux RISC-V SpacemiT Binding for 6.17 - Reset DT Binding for K1 SoC * tag 'spacemit-reset-binding-for-6.17-1': dt-bindings: soc: spacemit: define spacemit,k1-ccu resets Signed-off-by: Yixun Lan <dlan@gentoo.org>
This commit is contained in:
Yixun Lan
commit
aadc509afc
2 changed files with 163 additions and 7 deletions
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@ -19,6 +19,9 @@ properties:
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- spacemit,k1-syscon-apbc
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- spacemit,k1-syscon-apmu
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- spacemit,k1-syscon-mpmu
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- spacemit,k1-syscon-rcpu
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- spacemit,k1-syscon-rcpu2
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- spacemit,k1-syscon-apbc2
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reg:
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maxItems: 1
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@ -47,9 +50,6 @@ properties:
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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- "#reset-cells"
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allOf:
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@ -57,13 +57,28 @@ allOf:
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properties:
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compatible:
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contains:
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const: spacemit,k1-syscon-apbc
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enum:
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- spacemit,k1-syscon-apmu
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- spacemit,k1-syscon-mpmu
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then:
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properties:
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"#power-domain-cells": false
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else:
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required:
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- "#power-domain-cells"
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else:
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properties:
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"#power-domain-cells": false
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- if:
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properties:
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compatible:
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contains:
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enum:
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- spacemit,k1-syscon-apbc
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- spacemit,k1-syscon-apmu
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- spacemit,k1-syscon-mpmu
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then:
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required:
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- clocks
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- clock-names
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- "#clock-cells"
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additionalProperties: false
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@ -78,6 +78,9 @@
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#define CLK_APB 31
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#define CLK_WDT_BUS 32
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/* MPMU resets */
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#define RESET_WDT 0
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/* APBC clocks */
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#define CLK_UART0 0
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#define CLK_UART2 1
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@ -180,6 +183,59 @@
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#define CLK_TSEN_BUS 98
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#define CLK_IPC_AP2AUD_BUS 99
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/* APBC resets */
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#define RESET_UART0 0
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#define RESET_UART2 1
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#define RESET_UART3 2
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#define RESET_UART4 3
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#define RESET_UART5 4
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#define RESET_UART6 5
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#define RESET_UART7 6
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#define RESET_UART8 7
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#define RESET_UART9 8
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#define RESET_GPIO 9
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#define RESET_PWM0 10
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#define RESET_PWM1 11
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#define RESET_PWM2 12
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#define RESET_PWM3 13
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#define RESET_PWM4 14
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#define RESET_PWM5 15
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#define RESET_PWM6 16
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#define RESET_PWM7 17
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#define RESET_PWM8 18
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#define RESET_PWM9 19
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#define RESET_PWM10 20
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#define RESET_PWM11 21
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#define RESET_PWM12 22
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#define RESET_PWM13 23
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#define RESET_PWM14 24
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#define RESET_PWM15 25
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#define RESET_PWM16 26
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#define RESET_PWM17 27
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#define RESET_PWM18 28
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#define RESET_PWM19 29
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#define RESET_SSP3 30
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#define RESET_RTC 31
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#define RESET_TWSI0 32
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#define RESET_TWSI1 33
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#define RESET_TWSI2 34
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#define RESET_TWSI4 35
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#define RESET_TWSI5 36
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#define RESET_TWSI6 37
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#define RESET_TWSI7 38
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#define RESET_TWSI8 39
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#define RESET_TIMERS1 40
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#define RESET_TIMERS2 41
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#define RESET_AIB 42
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#define RESET_ONEWIRE 43
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#define RESET_SSPA0 44
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#define RESET_SSPA1 45
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#define RESET_DRO 46
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#define RESET_IR 47
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#define RESET_TSEN 48
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#define RESET_IPC_AP2AUD 49
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#define RESET_CAN0 50
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/* APMU clocks */
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#define CLK_CCI550 0
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#define CLK_CPU_C0_HI 1
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@ -244,4 +300,89 @@
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#define CLK_V2D 60
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#define CLK_EMMC_BUS 61
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/* APMU resets */
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#define RESET_CCIC_4X 0
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#define RESET_CCIC1_PHY 1
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#define RESET_SDH_AXI 2
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#define RESET_SDH0 3
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#define RESET_SDH1 4
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#define RESET_SDH2 5
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#define RESET_USBP1_AXI 6
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#define RESET_USB_AXI 7
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#define RESET_USB30_AHB 8
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#define RESET_USB30_VCC 9
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#define RESET_USB30_PHY 10
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#define RESET_QSPI 11
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#define RESET_QSPI_BUS 12
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#define RESET_DMA 13
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#define RESET_AES 14
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#define RESET_VPU 15
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#define RESET_GPU 16
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#define RESET_EMMC 17
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#define RESET_EMMC_X 18
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#define RESET_AUDIO_SYS 19
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#define RESET_AUDIO_MCU 20
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#define RESET_AUDIO_APMU 21
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#define RESET_HDMI 22
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#define RESET_PCIE0_MASTER 23
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#define RESET_PCIE0_SLAVE 24
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#define RESET_PCIE0_DBI 25
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#define RESET_PCIE0_GLOBAL 26
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#define RESET_PCIE1_MASTER 27
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#define RESET_PCIE1_SLAVE 28
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#define RESET_PCIE1_DBI 29
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#define RESET_PCIE1_GLOBAL 30
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#define RESET_PCIE2_MASTER 31
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#define RESET_PCIE2_SLAVE 32
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#define RESET_PCIE2_DBI 33
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#define RESET_PCIE2_GLOBAL 34
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#define RESET_EMAC0 35
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#define RESET_EMAC1 36
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#define RESET_JPG 37
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#define RESET_CCIC2PHY 38
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#define RESET_CCIC3PHY 39
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#define RESET_CSI 40
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#define RESET_ISP_CPP 41
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#define RESET_ISP_BUS 42
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#define RESET_ISP 43
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#define RESET_ISP_CI 44
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#define RESET_DPU_MCLK 45
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#define RESET_DPU_ESC 46
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#define RESET_DPU_HCLK 47
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#define RESET_DPU_SPIBUS 48
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#define RESET_DPU_SPI_HBUS 49
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#define RESET_V2D 50
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#define RESET_MIPI 51
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#define RESET_MC 52
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/* RCPU resets */
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#define RESET_RCPU_SSP0 0
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#define RESET_RCPU_I2C0 1
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#define RESET_RCPU_UART1 2
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#define RESET_RCPU_IR 3
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#define RESET_RCPU_CAN 4
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#define RESET_RCPU_UART0 5
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#define RESET_RCPU_HDMI_AUDIO 6
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/* RCPU2 resets */
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#define RESET_RCPU2_PWM0 0
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#define RESET_RCPU2_PWM1 1
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#define RESET_RCPU2_PWM2 2
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#define RESET_RCPU2_PWM3 3
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#define RESET_RCPU2_PWM4 4
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#define RESET_RCPU2_PWM5 5
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#define RESET_RCPU2_PWM6 6
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#define RESET_RCPU2_PWM7 7
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#define RESET_RCPU2_PWM8 8
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#define RESET_RCPU2_PWM9 9
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/* APBC2 resets */
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#define RESET_APBC2_UART1 0
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#define RESET_APBC2_SSP2 1
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#define RESET_APBC2_TWSI3 2
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#define RESET_APBC2_RTC 3
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#define RESET_APBC2_TIMERS0 4
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#define RESET_APBC2_KPC 5
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#define RESET_APBC2_GPIO 6
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#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */
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