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dt-bindings: PCI: dwc: Add max-functions EP property

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In accordance with [1] the CX_NFUNC IP-core synthesize parameter is
responsible for the number of physical functions to support in the EP
mode. Its upper limit is 32. Let's use it to constrain the number of
PCIe functions the DW PCIe EP DT-nodes can advertise.

[1] Synopsys DesignWare Cores PCI Express Controller Databook - DWC PCIe
Endpoint, Version 5.40a, March 2019, p. 887.

Link: https://lore.kernel.org/r/20221113191301.5526-9-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Serge Semin 2022-11-13 22:12:49 +03:00 • committed by Lorenzo Pieralisi
parent f133396e2d
commit 12f7936c7a
1 changed files with 4 additions and 0 deletions
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4
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
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@ -41,6 +41,9 @@ properties:
items:
enum: [dbi, dbi2, config, atu, addr_space, link, atu_dma, appl]
max-functions:
maximum: 32
required:
- compatible
- reg
@ -61,4 +64,5 @@ examples:
phy-names = "pcie0", "pcie1", "pcie2", "pcie3";
max-link-speed = <3>;
max-functions = /bits/ 8 <4>;
};