linux/include/dt-bindings/clock/renesas,r9a09g057-cpg.h

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 *
 * Copyright (C) 2024 Renesas Electronics Corp.
 */
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* Core Clock list */
#define R9A09G057_SYS_0_PCLK			0
#define R9A09G057_CA55_0_CORE_CLK0		1
#define R9A09G057_CA55_0_CORE_CLK1		2
#define R9A09G057_CA55_0_CORE_CLK2		3
#define R9A09G057_CA55_0_CORE_CLK3		4
#define R9A09G057_CA55_0_PERIPHCLK		5
#define R9A09G057_CM33_CLK0			6
#define R9A09G057_CST_0_SWCLKTCK		7
#define R9A09G057_IOTOP_0_SHCLK			8
#define R9A09G057_USB2_0_CLK_CORE0		9
#define R9A09G057_USB2_0_CLK_CORE1		10
#define R9A09G057_GBETH_0_CLK_PTP_REF_I		11
#define R9A09G057_GBETH_1_CLK_PTP_REF_I		12
#define R9A09G057_SPI_CLK_SPI			13

#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */
dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG Document the device tree bindings for the Renesas RZ/V2H(P) SoC Clock Pulse Generator (CPG). CPG block handles the below operations: - Generation and control of clock signals for the IP modules - Generation and control of resets - Control over booting - Low power consumption and power supply domains Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the core clocks are a subset of the ones which are listed as part of section 4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240729202645.263525-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2024-07-29 21:26:43 +01:00			`/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)`
			`*`
			`* Copyright (C) 2024 Renesas Electronics Corp.`
			`*/`
			`#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__`
			`#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__`

			`#include <dt-bindings/clock/renesas-cpg-mssr.h>`

			`/* Core Clock list */`
			`#define R9A09G057_SYS_0_PCLK 0`
			`#define R9A09G057_CA55_0_CORE_CLK0 1`
			`#define R9A09G057_CA55_0_CORE_CLK1 2`
			`#define R9A09G057_CA55_0_CORE_CLK2 3`
			`#define R9A09G057_CA55_0_CORE_CLK3 4`
			`#define R9A09G057_CA55_0_PERIPHCLK 5`
			`#define R9A09G057_CM33_CLK0 6`
			`#define R9A09G057_CST_0_SWCLKTCK 7`
			`#define R9A09G057_IOTOP_0_SHCLK 8`
dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks Add definitions for USB2 PHY core clocks and Gigabit Ethernet PTP reference core clocks in the R9A09G057 CPG DT bindings header file. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407165202.197570-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2025-04-07 17:52:00 +01:00			`#define R9A09G057_USB2_0_CLK_CORE0 9`
			`#define R9A09G057_USB2_0_CLK_CORE1 10`
			`#define R9A09G057_GBETH_0_CLK_PTP_REF_I 11`
			`#define R9A09G057_GBETH_1_CLK_PTP_REF_I 12`
dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock Add XSPI core clock definitions to the clock bindings for the Renesas R9A09G056 and R9A09G057 SoCs. These clocks IDs are used to support XSPI interface. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250627204237.214635-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2025-06-27 21:42:32 +01:00			`#define R9A09G057_SPI_CLK_SPI 13`
dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG Document the device tree bindings for the Renesas RZ/V2H(P) SoC Clock Pulse Generator (CPG). CPG block handles the below operations: - Generation and control of clock signals for the IP modules - Generation and control of resets - Control over booting - Low power consumption and power supply domains Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the core clocks are a subset of the ones which are listed as part of section 4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240729202645.263525-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2024-07-29 21:26:43 +01:00
			`#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */`