2019-05-19 13:07:45 +01:00
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# SPDX-License-Identifier: GPL-2.0-only
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2005-07-30 19:31:23 -04:00
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#
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# PHY Layer Configuration
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#
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phylink: add phylink infrastructure
The link between the ethernet MAC and its PHY has become more complex
as the interface evolves. This is especially true with serdes links,
where the part of the PHY is effectively integrated into the MAC.
Serdes links can be connected to a variety of devices, including SFF
modules soldered down onto the board with the MAC, a SFP cage with
a hotpluggable SFP module which may contain a PHY or directly modulate
the serdes signals onto optical media with or without a PHY, or even
a classical PHY connection.
Moreover, the negotiation information on serdes links comes in two
varieties - SGMII mode, where the PHY provides its speed/duplex/flow
control information to the MAC, and 1000base-X mode where both ends
exchange their abilities and each resolve the link capabilities.
This means we need a more flexible means to support these arrangements,
particularly with the hotpluggable nature of SFP, where the PHY can
be attached or detached after the network device has been brought up.
Ethtool information can come from multiple sources:
- we may have a PHY operating in either SGMII or 1000base-X mode, in
which case we take ethtool/mii data directly from the PHY.
- we may have a optical SFP module without a PHY, with the MAC
operating in 1000base-X mode - the ethtool/mii data needs to come
from the MAC.
- we may have a copper SFP module with a PHY whic can't be accessed,
which means we need to take ethtool/mii data from the MAC.
Phylink aims to solve this by providing an intermediary between the
MAC and PHY, providing a safe way for PHYs to be hotplugged, and
allowing a SFP driver to reconfigure the serdes connection.
Phylink also takes over support of fixed link connections, where the
speed/duplex/flow control are fixed, but link status may be controlled
by a GPIO signal. By avoiding the fixed-phy implementation, phylink
can provide a faster response to link events: fixed-phy has to wait for
phylib to operate its state machine, which can take several seconds.
In comparison, phylink takes milliseconds.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
- remove sync status
- rework supported and advertisment handling
- add 1000base-x speed for fixed links
- use functionality exported from phy-core, reworking
__phylink_ethtool_ksettings_set for it
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-07-25 15:03:13 +01:00
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config PHYLINK
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tristate
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select PHYLIB
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select SWPHY
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help
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PHYlink models the link between the PHY and MAC, allowing fixed
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configuration links, PHYs, and Serdes links with MAC level
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autonegotiation modes.
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2017-09-18 14:59:20 +02:00
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menuconfig PHYLIB
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2018-04-27 12:41:49 -07:00
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tristate "PHY Device support and infrastructure"
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2025-05-15 10:11:54 +02:00
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select MDIO_BUS
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2017-09-18 14:59:20 +02:00
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help
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Ethernet controllers are usually attached to PHY
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devices. This option provides infrastructure for
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managing PHY devices.
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2017-03-23 10:01:19 -07:00
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if PHYLIB
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config SWPHY
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bool
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2025-06-12 23:28:18 +02:00
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config PHY_PACKAGE
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tristate
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2017-03-23 10:01:19 -07:00
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config LED_TRIGGER_PHY
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bool "Support LED triggers for tracking link state"
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depends on LEDS_TRIGGERS
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2020-06-14 01:50:22 +09:00
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help
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2017-03-23 10:01:19 -07:00
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Adds support for a set of LED trigger events per-PHY. Link
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state change will trigger the events, for consumption by an
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LED class driver. There are triggers for each link speed currently
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2017-11-02 00:49:18 +01:00
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supported by the PHY and also a one common "link" trigger as a
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logical-or of all the link speed ones.
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All these triggers are named according to the following pattern:
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2017-08-14 15:43:00 +02:00
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<mii bus id>:<phy>:<speed>
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2017-03-23 10:01:19 -07:00
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Where speed is in the form:
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2017-11-02 00:49:18 +01:00
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<Speed in megabits>Mbps OR <Speed in gigabits>Gbps OR link
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for any speed known to the PHY.
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2017-03-23 10:01:19 -07:00
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2024-08-12 09:30:45 +02:00
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config OPEN_ALLIANCE_HELPERS
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bool
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2023-04-20 10:45:51 +02:00
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config PHYLIB_LEDS
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2023-04-26 10:15:31 +02:00
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def_bool OF
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2023-04-20 10:45:51 +02:00
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depends on LEDS_CLASS=y || LEDS_CLASS=PHYLIB
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help
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When LED class support is enabled, phylib can automatically
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probe LED setting from device tree.
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2017-03-23 10:01:19 -07:00
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2020-08-27 04:00:32 +02:00
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config FIXED_PHY
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tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
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select SWPHY
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help
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Adds the platform "fixed" MDIO Bus to cover the boards that use
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PHYs that are not connected to the real MDIO bus.
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Currently tested with mpc866ads and mpc8349e-mitx.
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2016-08-18 23:56:05 +02:00
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2023-12-13 09:42:08 +09:00
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config RUST_PHYLIB_ABSTRACTIONS
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bool "Rust PHYLIB abstractions support"
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depends on RUST
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depends on PHYLIB=y
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help
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Adds support needed for PHY drivers written in Rust. It provides
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a wrapper around the C phylib core.
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2017-07-25 15:03:39 +01:00
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config SFP
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tristate "SFP cage support"
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depends on I2C && PHYLINK
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2018-07-19 09:41:39 -07:00
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depends on HWMON || HWMON=n
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2017-07-25 15:03:39 +01:00
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select MDIO_I2C
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2020-08-27 04:00:32 +02:00
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comment "MII PHY device drivers"
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net: phy: Add support for Aeonsemi AS21xxx PHYs
Add support for Aeonsemi AS21xxx 10G C45 PHYs. These PHYs integrate
an IPC to setup some configuration and require special handling to
sync with the parity bit. The parity bit is a way the IPC use to
follow correct order of command sent.
Supported PHYs AS21011JB1, AS21011PB1, AS21010JB1, AS21010PB1,
AS21511JB1, AS21511PB1, AS21510JB1, AS21510PB1, AS21210JB1,
AS21210PB1 that all register with the PHY ID 0x7500 0x7510
before the firmware is loaded.
They all support up to 5 LEDs with various HW mode supported.
While implementing it was found some strange coincidence with using the
same logic for implementing C22 in MMD regs in Broadcom PHYs.
For reference here the AS21xxx PHY name logic:
AS21x1xxB1
^ ^^
| |J: Supports SyncE/PTP
| |P: No SyncE/PTP support
| 1: Supports 2nd Serdes
| 2: Not 2nd Serdes support
0: 10G, 5G, 2.5G
5: 5G, 2.5G
2: 2.5G
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://patch.msgid.link/20250517201353.5137-6-ansuelsmth@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-05-17 22:13:49 +02:00
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config AS21XXX_PHY
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tristate "Aeonsemi AS21xxx PHYs"
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help
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Currently supports the Aeonsemi AS21xxx PHY.
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These are C45 PHYs 10G that require all a generic firmware.
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Supported PHYs AS21011JB1, AS21011PB1, AS21010JB1, AS21010PB1,
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AS21511JB1, AS21511PB1, AS21510JB1, AS21510PB1, AS21210JB1,
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AS21210PB1 that all register with the PHY ID 0x7500 0x7500
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before the firmware is loaded.
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2024-03-26 17:23:05 +01:00
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config AIR_EN8811H_PHY
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tristate "Airoha EN8811H 2.5 Gigabit PHY"
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help
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Currently supports the Airoha EN8811H PHY.
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2020-08-27 04:00:32 +02:00
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config AMD_PHY
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2023-09-24 10:19:02 +02:00
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tristate "AMD and Altima PHYs"
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2020-08-27 04:00:32 +02:00
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help
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2023-09-24 10:19:02 +02:00
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Currently supports the AMD am79c874 and Altima AC101L.
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2020-08-27 04:00:32 +02:00
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config MESON_GXL_PHY
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tristate "Amlogic Meson GXL Internal PHY"
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depends on ARCH_MESON || COMPILE_TEST
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2023-03-18 21:36:04 +01:00
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select SMSC_PHY
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2020-08-27 04:00:32 +02:00
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help
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Currently has a driver for the Amlogic Meson GXL Internal PHY
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2019-08-16 16:09:59 +03:00
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config ADIN_PHY
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tristate "Analog Devices Industrial Ethernet PHYs"
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help
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Adds support for the Analog Devices Industrial Ethernet PHYs.
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Currently supports the:
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- ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
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- ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
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Ethernet PHY
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2022-04-29 18:34:35 +03:00
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config ADIN1100_PHY
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tristate "Analog Devices Industrial Ethernet T1L PHYs"
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help
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Adds support for the Analog Devices Industrial T1L Ethernet PHYs.
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Currently supports the:
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- ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
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2024-08-28 07:35:16 +00:00
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config AMCC_QT2025_PHY
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tristate "AMCC QT2025 PHY"
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depends on RUST_PHYLIB_ABSTRACTIONS
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depends on RUST_FW_LOADER_ABSTRACTIONS
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help
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Adds support for the Applied Micro Circuits Corporation QT2025 PHY.
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2023-11-14 15:08:41 +01:00
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source "drivers/net/phy/aquantia/Kconfig"
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2016-08-18 23:56:05 +02:00
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2019-06-07 17:37:34 +12:00
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config AX88796B_PHY
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2018-04-19 14:05:18 +12:00
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tristate "Asix PHYs"
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help
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Currently supports the Asix Electronics PHY found in the X-Surf 100
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AX88796B package.
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2023-12-13 09:42:11 +09:00
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config AX88796B_RUST_PHY
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bool "Rust reference driver for Asix PHYs"
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depends on RUST_PHYLIB_ABSTRACTIONS && AX88796B_PHY
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help
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Uses the Rust reference driver for Asix PHYs (ax88796b_rust.ko).
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The features are equivalent. It supports the Asix Electronics PHY
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found in the X-Surf 100 AX88796B package.
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2020-08-27 04:00:32 +02:00
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config BROADCOM_PHY
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tristate "Broadcom 54XX PHYs"
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select BCM_NET_PHYLIB
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2022-06-21 22:04:53 -07:00
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select BCM_NET_PHYPTP if NETWORK_PHY_TIMESTAMPING
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depends on PTP_1588_CLOCK_OPTIONAL
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2020-08-27 04:00:32 +02:00
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help
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Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
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BCM5481, BCM54810 and BCM5482 PHYs.
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config BCM54140_PHY
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tristate "Broadcom BCM54140 PHY"
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depends on HWMON || HWMON=n
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select BCM_NET_PHYLIB
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2025-06-12 23:28:18 +02:00
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select PHY_PACKAGE
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2020-08-27 04:00:32 +02:00
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help
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Support the Broadcom BCM54140 Quad SGMII/QSGMII PHY.
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This driver also supports the hardware monitoring of this PHY and
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exposes voltage and temperature sensors.
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2009-07-01 01:29:36 +00:00
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config BCM63XX_PHY
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2016-08-18 23:56:06 +02:00
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tristate "Broadcom 63xx SOCs internal PHY"
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2018-09-12 01:53:10 +02:00
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depends on BCM63XX || COMPILE_TEST
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2015-10-06 12:25:48 -07:00
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select BCM_NET_PHYLIB
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2020-06-14 01:50:22 +09:00
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help
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2009-07-01 01:29:36 +00:00
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Currently supports the 6348 and 6358 PHYs.
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2014-02-13 16:08:45 -08:00
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config BCM7XXX_PHY
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2016-08-18 23:56:06 +02:00
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tristate "Broadcom 7xxx SOCs internal PHYs"
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2015-10-06 12:25:48 -07:00
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select BCM_NET_PHYLIB
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2020-06-14 01:50:22 +09:00
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help
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2014-02-13 16:08:45 -08:00
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Currently supports the BCM7366, BCM7439, BCM7445, and
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40nm and 65nm generation of BCM7xxx Set Top Box SoCs.
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2020-08-27 04:00:32 +02:00
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config BCM84881_PHY
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tristate "Broadcom BCM84881 PHY"
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help
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Support the Broadcom BCM84881 PHY.
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2012-06-27 07:33:38 +00:00
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config BCM87XX_PHY
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2016-08-18 23:56:06 +02:00
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tristate "Broadcom BCM8706 and BCM8727 PHYs"
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2012-06-27 07:33:38 +00:00
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help
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Currently supports the BCM8706 and BCM8727 10G Ethernet PHYs.
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2016-08-18 23:56:05 +02:00
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config BCM_CYGNUS_PHY
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2019-03-21 16:23:30 -07:00
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tristate "Broadcom Cygnus/Omega SoC internal PHY"
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2019-03-20 12:53:13 -07:00
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depends on ARCH_BCM_IPROC || COMPILE_TEST
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2016-08-18 23:56:05 +02:00
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depends on MDIO_BCM_IPROC
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select BCM_NET_PHYLIB
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2020-06-14 01:50:22 +09:00
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help
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2016-08-18 23:56:05 +02:00
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This PHY driver is for the 1G internal PHYs of the Broadcom
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2019-03-20 12:53:13 -07:00
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Cygnus and Omega Family SoC.
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2007-05-11 18:24:51 -05:00
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2016-08-18 23:56:05 +02:00
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Currently supports internal PHY's used in the BCM11300,
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BCM11320, BCM11350, BCM11360, BCM58300, BCM58302,
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BCM58303 & BCM58305 Broadcom Cygnus SoCs.
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2008-02-03 03:50:54 -08:00
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2016-08-18 23:56:05 +02:00
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config BCM_NET_PHYLIB
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tristate
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2008-11-28 16:14:12 -08:00
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2022-06-21 22:04:53 -07:00
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config BCM_NET_PHYPTP
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tristate
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2016-08-18 23:56:05 +02:00
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config CICADA_PHY
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2016-08-18 23:56:06 +02:00
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tristate "Cicada PHYs"
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2020-06-14 01:50:22 +09:00
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help
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2016-08-18 23:56:05 +02:00
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Currently supports the cis8204
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2008-12-09 22:21:25 -08:00
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2017-05-29 09:11:30 +00:00
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config CORTINA_PHY
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tristate "Cortina EDC CDR 10G Ethernet PHY"
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2020-06-14 01:50:22 +09:00
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help
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2017-05-29 09:11:30 +00:00
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Currently supports the CS4340 phy.
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2016-08-18 23:56:05 +02:00
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config DAVICOM_PHY
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2016-08-18 23:56:06 +02:00
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tristate "Davicom PHYs"
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2020-06-14 01:50:22 +09:00
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help
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2016-08-18 23:56:05 +02:00
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Currently supports dm9161e and dm9131
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2010-04-29 06:12:41 +00:00
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2016-08-18 23:56:05 +02:00
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config ICPLUS_PHY
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2016-08-18 23:56:06 +02:00
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tristate "ICPlus PHYs"
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2020-06-14 01:50:22 +09:00
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help
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2016-08-18 23:56:05 +02:00
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Currently supports the IP175C and IP1001 PHYs.
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2015-10-06 12:25:47 -07:00
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2020-08-27 04:00:32 +02:00
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config LXT_PHY
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tristate "Intel LXT PHYs"
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help
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Currently supports the lxt970, lxt971
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2016-06-05 23:41:11 +02:00
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config INTEL_XWAY_PHY
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2016-08-18 23:56:06 +02:00
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tristate "Intel XWAY PHYs"
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2020-06-14 01:50:22 +09:00
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help
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2016-06-05 23:41:11 +02:00
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Supports the Intel XWAY (former Lantiq) 11G and 22E PHYs.
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These PHYs are marked as standalone chips under the names
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PEF 7061, PEF 7071 and PEF 7072 or integrated into the Intel
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SoCs xRX200, xRX300, xRX330, xRX350 and xRX550.
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2016-08-18 23:56:05 +02:00
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config LSI_ET1011C_PHY
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2016-08-18 23:56:06 +02:00
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tristate "LSI ET1011C PHY"
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2020-06-14 01:50:22 +09:00
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help
|
2016-08-18 23:56:05 +02:00
|
|
|
Supports the LSI ET1011C PHY.
|
2016-07-15 16:26:33 +08:00
|
|
|
|
2016-08-18 23:56:05 +02:00
|
|
|
config MARVELL_PHY
|
2020-08-27 04:00:32 +02:00
|
|
|
tristate "Marvell Alaska PHYs"
|
2020-06-14 01:50:22 +09:00
|
|
|
help
|
2020-08-27 04:00:32 +02:00
|
|
|
Currently has a driver for the 88E1XXX
|
2016-08-18 23:56:05 +02:00
|
|
|
|
2017-06-05 12:23:16 +01:00
|
|
|
config MARVELL_10G_PHY
|
|
|
|
tristate "Marvell Alaska 10Gbit PHYs"
|
2020-06-14 01:50:22 +09:00
|
|
|
help
|
2017-06-05 12:23:16 +01:00
|
|
|
Support for the Marvell Alaska MV88X3310 and compatible PHYs.
|
|
|
|
|
2023-07-19 08:42:58 +02:00
|
|
|
config MARVELL_88Q2XXX_PHY
|
|
|
|
tristate "Marvell 88Q2XXX PHY"
|
2024-02-18 08:57:45 +01:00
|
|
|
depends on HWMON || HWMON=n
|
2023-07-19 08:42:58 +02:00
|
|
|
help
|
|
|
|
Support for the Marvell 88Q2XXX 100/1000BASE-T1 Automotive Ethernet
|
|
|
|
PHYs.
|
|
|
|
|
2021-03-15 17:19:26 +03:00
|
|
|
config MARVELL_88X2222_PHY
|
|
|
|
tristate "Marvell 88X2222 PHY"
|
|
|
|
help
|
|
|
|
Support for the Marvell 88X2222 Dual-port Multi-speed Ethernet
|
|
|
|
Transceiver.
|
|
|
|
|
2021-07-19 13:32:12 +08:00
|
|
|
config MAXLINEAR_GPHY
|
|
|
|
tristate "Maxlinear Ethernet PHYs"
|
2022-06-22 16:17:16 +02:00
|
|
|
select POLYNOMIAL if HWMON
|
|
|
|
depends on HWMON || HWMON=n
|
2021-07-19 13:32:12 +08:00
|
|
|
help
|
|
|
|
Support for the Maxlinear GPY115, GPY211, GPY212, GPY215,
|
|
|
|
GPY241, GPY245 PHYs.
|
|
|
|
|
2025-05-21 23:28:15 +02:00
|
|
|
config MAXLINEAR_86110_PHY
|
|
|
|
tristate "MaxLinear MXL86110 PHY support"
|
|
|
|
help
|
|
|
|
Support for the MaxLinear MXL86110 Gigabit Ethernet
|
|
|
|
Physical Layer transceiver.
|
|
|
|
The MXL86110 is commonly used in networking equipment such as
|
|
|
|
routers, switches, and embedded systems, providing the
|
|
|
|
physical interface for 10/100/1000 Mbps Ethernet connections
|
|
|
|
over copper media.
|
|
|
|
If you are using a board with the MXL86110 PHY connected to your
|
|
|
|
Ethernet MAC, you should enable this option.
|
|
|
|
|
2024-11-09 00:34:51 +08:00
|
|
|
source "drivers/net/phy/mediatek/Kconfig"
|
2023-06-11 00:48:10 +01:00
|
|
|
|
2016-08-18 23:56:05 +02:00
|
|
|
config MICREL_PHY
|
2016-08-18 23:56:06 +02:00
|
|
|
tristate "Micrel PHYs"
|
2022-03-14 12:02:54 +01:00
|
|
|
depends on PTP_1588_CLOCK_OPTIONAL
|
2025-06-12 23:28:18 +02:00
|
|
|
select PHY_PACKAGE
|
2020-06-14 01:50:22 +09:00
|
|
|
help
|
2016-08-18 23:56:05 +02:00
|
|
|
Supports the KSZ9021, VSC8201, KS8001 PHYs.
|
|
|
|
|
2023-04-21 18:38:54 +02:00
|
|
|
config MICROCHIP_T1S_PHY
|
2023-05-26 20:53:43 +05:30
|
|
|
tristate "Microchip 10BASE-T1S Ethernet PHYs"
|
2023-04-21 18:38:54 +02:00
|
|
|
help
|
2024-10-10 13:52:04 +05:30
|
|
|
Currently supports the LAN8670/1/2 Rev.B1/C1/C2 and
|
|
|
|
LAN8650/1 Rev.B0/B1 Internal PHYs.
|
2023-04-21 18:38:54 +02:00
|
|
|
|
2016-08-18 23:56:05 +02:00
|
|
|
config MICROCHIP_PHY
|
2016-08-18 23:56:06 +02:00
|
|
|
tristate "Microchip PHYs"
|
2016-07-25 17:12:40 -07:00
|
|
|
help
|
2016-08-18 23:56:05 +02:00
|
|
|
Supports the LAN88XX PHYs.
|
2016-07-25 17:12:40 -07:00
|
|
|
|
2018-05-02 21:09:17 +05:30
|
|
|
config MICROCHIP_T1_PHY
|
|
|
|
tristate "Microchip T1 PHYs"
|
2025-01-10 11:14:24 +05:30
|
|
|
select MICROCHIP_PHY_RDS_PTP if NETWORK_PHY_TIMESTAMPING
|
|
|
|
depends on PTP_1588_CLOCK_OPTIONAL
|
2020-06-14 01:50:22 +09:00
|
|
|
help
|
2024-12-19 18:03:09 +05:30
|
|
|
Supports the LAN8XXX PHYs.
|
|
|
|
|
|
|
|
config MICROCHIP_PHY_RDS_PTP
|
|
|
|
tristate
|
|
|
|
help
|
|
|
|
Currently supports LAN887X T1 PHY
|
2018-05-02 21:09:17 +05:30
|
|
|
|
2016-08-05 17:54:21 +05:30
|
|
|
config MICROSEMI_PHY
|
2016-09-08 14:09:31 +05:30
|
|
|
tristate "Microsemi PHYs"
|
2020-01-13 23:31:46 +01:00
|
|
|
depends on MACSEC || MACSEC=n
|
ethernet: fix PTP_1588_CLOCK dependencies
The 'imply' keyword does not do what most people think it does, it only
politely asks Kconfig to turn on another symbol, but does not prevent
it from being disabled manually or built as a loadable module when the
user is built-in. In the ICE driver, the latter now causes a link failure:
aarch64-linux-ld: drivers/net/ethernet/intel/ice/ice_main.o: in function `ice_eth_ioctl':
ice_main.c:(.text+0x13b0): undefined reference to `ice_ptp_get_ts_config'
ice_main.c:(.text+0x13b0): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `ice_ptp_get_ts_config'
aarch64-linux-ld: ice_main.c:(.text+0x13bc): undefined reference to `ice_ptp_set_ts_config'
ice_main.c:(.text+0x13bc): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `ice_ptp_set_ts_config'
aarch64-linux-ld: drivers/net/ethernet/intel/ice/ice_main.o: in function `ice_prepare_for_reset':
ice_main.c:(.text+0x31fc): undefined reference to `ice_ptp_release'
ice_main.c:(.text+0x31fc): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `ice_ptp_release'
aarch64-linux-ld: drivers/net/ethernet/intel/ice/ice_main.o: in function `ice_rebuild':
This is a recurring problem in many drivers, and we have discussed
it several times befores, without reaching a consensus. I'm providing
a link to the previous email thread for reference, which discusses
some related problems.
To solve the dependency issue better than the 'imply' keyword, introduce a
separate Kconfig symbol "CONFIG_PTP_1588_CLOCK_OPTIONAL" that any driver
can depend on if it is able to use PTP support when available, but works
fine without it. Whenever CONFIG_PTP_1588_CLOCK=m, those drivers are
then prevented from being built-in, the same way as with a 'depends on
PTP_1588_CLOCK || !PTP_1588_CLOCK' dependency that does the same trick,
but that can be rather confusing when you first see it.
Since this should cover the dependencies correctly, the IS_REACHABLE()
hack in the header is no longer needed now, and can be turned back
into a normal IS_ENABLED() check. Any driver that gets the dependency
wrong will now cause a link time failure rather than being unable to use
PTP support when that is in a loadable module.
However, the two recently added ptp_get_vclocks_index() and
ptp_convert_timestamp() interfaces are only called from builtin code with
ethtool and socket timestamps, so keep the current behavior by stubbing
those out completely when PTP is in a loadable module. This should be
addressed properly in a follow-up.
As Richard suggested, we may want to actually turn PTP support into a
'bool' option later on, preventing it from being a loadable module
altogether, which would be one way to solve the problem with the ethtool
interface.
Fixes: 06c16d89d2cb ("ice: register 1588 PTP clock device object for E810 devices")
Link: https://lore.kernel.org/netdev/20210804121318.337276-1-arnd@kernel.org/
Link: https://lore.kernel.org/netdev/CAK8P3a06enZOf=XyZ+zcAwBczv41UuCTz+=0FMf2gBz1_cOnZQ@mail.gmail.com/
Link: https://lore.kernel.org/netdev/CAK8P3a3=eOxE-K25754+fB_-i_0BZzf9a9RfPTX3ppSwu9WZXw@mail.gmail.com/
Link: https://lore.kernel.org/netdev/20210726084540.3282344-1-arnd@kernel.org/
Acked-by: Shannon Nelson <snelson@pensando.io>
Acked-by: Jacob Keller <jacob.e.keller@intel.com>
Acked-by: Richard Cochran <richardcochran@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210812183509.1362782-1-arnd@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-08-12 20:33:58 +02:00
|
|
|
depends on PTP_1588_CLOCK_OPTIONAL || !NETWORK_PHY_TIMESTAMPING
|
2020-06-25 09:18:16 +02:00
|
|
|
select CRYPTO_LIB_AES if MACSEC
|
2025-06-12 23:28:18 +02:00
|
|
|
select PHY_PACKAGE
|
2020-06-14 01:50:22 +09:00
|
|
|
help
|
net: phy: mscc: add support for VSC8514 PHY.
The VSC8514 PHY is a 4-ports PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X, can communicate with the MAC via QSGMII.
The MAC interface protocol for each port within QSGMII can
be either 1000BASE-X or SGMII, if the QSGMII MAC that the VSC8514 is
connecting to supports this functionality.
VSC8514 also supports SGMII MAC-side autonegotiation on each individual
port, downshifting, can set the blinking pattern of each of its 4 LEDs,
SyncE, 1000BASE-T Ring Resiliency as well as HP Auto-MDIX detection.
This adds support for 10BASE-T, 100BASE-TX, and 1000BASE-T,
QSGMII link with the MAC, downshifting, HP Auto-MDIX detection
and blinking pattern for its 4 LEDs.
The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.
If the PHYs haven't been reset before booting the Linux kernel and were
configured to use interrupts for e.g. link status updates, it is
required to clear the interrupts mask register of all PHYs before being
able to use interrupts with any PHY. The first PHY of the package that
will be init will take care of clearing all PHYs interrupts mask
registers. Thus, we need to keep track of the init sequence in the
package, if it's already been done or if it's to be done.
Most of the init sequence of a PHY of the package is common to all PHYs
in the package, thus we use the SMI broadcast feature which enables us
to propagate a write in one register of one PHY to all PHYs in the same
package.
Signed-off-by: Kavya Sree Kotagiri <kavyasree.kotagiri@microchip.com>
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Co-developed-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-22 11:51:35 +00:00
|
|
|
Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
|
2016-08-05 17:54:21 +05:30
|
|
|
|
2021-05-20 12:32:30 -04:00
|
|
|
config MOTORCOMM_PHY
|
|
|
|
tristate "Motorcomm PHYs"
|
|
|
|
help
|
|
|
|
Enables support for Motorcomm network PHYs.
|
2023-02-02 11:00:37 +08:00
|
|
|
Currently supports YT85xx Gigabit Ethernet PHYs.
|
2021-05-20 12:32:30 -04:00
|
|
|
|
2016-08-18 23:56:05 +02:00
|
|
|
config NATIONAL_PHY
|
2016-08-18 23:56:06 +02:00
|
|
|
tristate "National Semiconductor PHYs"
|
2020-06-14 01:50:22 +09:00
|
|
|
help
|
2016-08-18 23:56:05 +02:00
|
|
|
Currently supports the DP83865 PHY.
|
|
|
|
|
net: phy: add basic driver for NXP CBTX PHY
The CBTX PHY is a Fast Ethernet PHY integrated into the SJA1110 A/B/C
automotive Ethernet switches.
It was hoped it would work with the Generic PHY driver, but alas, it
doesn't. The most important reason why is that the PHY is powered down
by default, and it needs a vendor register to power it on.
It has a linear memory map that is accessed over SPI by the SJA1110
switch driver, which exposes a fake MDIO controller. It has the
following (and only the following) standard clause 22 registers:
0x0: MII_BMCR
0x1: MII_BMSR
0x2: MII_PHYSID1
0x3: MII_PHYSID2
0x4: MII_ADVERTISE
0x5: MII_LPA
0x6: MII_EXPANSION
0x7: the missing MII_NPAGE for Next Page Transmit Register
Every other register is vendor-defined.
The register map expands the standard clause 22 5-bit address space of
0x20 registers, however the driver does not need to access the extra
registers for now (and hopefully never). If it ever needs to do that, it
is possible to implement a fake (software) page switching mechanism
between the PHY driver and the SJA1110 MDIO controller driver.
Also, Auto-MDIX is turned off by default in hardware, the driver turns
it on by default and reports the current status. I've tested this with a
VSC8514 link partner and a crossover cable, by forcing the mode on the
link partner, and seeing that the CBTX PHY always sees the reverse of
the mode forced on the VSC8514 (and that traffic works). The link
doesn't come up (as expected) if MDI modes are forced on both ends in
the same way (with the cross-over cable, that is).
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20230418190141.1040562-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2023-04-18 22:01:41 +03:00
|
|
|
config NXP_CBTX_PHY
|
|
|
|
tristate "NXP 100BASE-TX PHYs"
|
|
|
|
help
|
|
|
|
Support the 100BASE-TX PHY integrated on the SJA1110 automotive
|
|
|
|
switch family.
|
|
|
|
|
2021-04-19 19:14:00 +03:00
|
|
|
config NXP_C45_TJA11XX_PHY
|
|
|
|
tristate "NXP C45 TJA11XX PHYs"
|
ethernet: fix PTP_1588_CLOCK dependencies
The 'imply' keyword does not do what most people think it does, it only
politely asks Kconfig to turn on another symbol, but does not prevent
it from being disabled manually or built as a loadable module when the
user is built-in. In the ICE driver, the latter now causes a link failure:
aarch64-linux-ld: drivers/net/ethernet/intel/ice/ice_main.o: in function `ice_eth_ioctl':
ice_main.c:(.text+0x13b0): undefined reference to `ice_ptp_get_ts_config'
ice_main.c:(.text+0x13b0): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `ice_ptp_get_ts_config'
aarch64-linux-ld: ice_main.c:(.text+0x13bc): undefined reference to `ice_ptp_set_ts_config'
ice_main.c:(.text+0x13bc): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `ice_ptp_set_ts_config'
aarch64-linux-ld: drivers/net/ethernet/intel/ice/ice_main.o: in function `ice_prepare_for_reset':
ice_main.c:(.text+0x31fc): undefined reference to `ice_ptp_release'
ice_main.c:(.text+0x31fc): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `ice_ptp_release'
aarch64-linux-ld: drivers/net/ethernet/intel/ice/ice_main.o: in function `ice_rebuild':
This is a recurring problem in many drivers, and we have discussed
it several times befores, without reaching a consensus. I'm providing
a link to the previous email thread for reference, which discusses
some related problems.
To solve the dependency issue better than the 'imply' keyword, introduce a
separate Kconfig symbol "CONFIG_PTP_1588_CLOCK_OPTIONAL" that any driver
can depend on if it is able to use PTP support when available, but works
fine without it. Whenever CONFIG_PTP_1588_CLOCK=m, those drivers are
then prevented from being built-in, the same way as with a 'depends on
PTP_1588_CLOCK || !PTP_1588_CLOCK' dependency that does the same trick,
but that can be rather confusing when you first see it.
Since this should cover the dependencies correctly, the IS_REACHABLE()
hack in the header is no longer needed now, and can be turned back
into a normal IS_ENABLED() check. Any driver that gets the dependency
wrong will now cause a link time failure rather than being unable to use
PTP support when that is in a loadable module.
However, the two recently added ptp_get_vclocks_index() and
ptp_convert_timestamp() interfaces are only called from builtin code with
ethtool and socket timestamps, so keep the current behavior by stubbing
those out completely when PTP is in a loadable module. This should be
addressed properly in a follow-up.
As Richard suggested, we may want to actually turn PTP support into a
'bool' option later on, preventing it from being a loadable module
altogether, which would be one way to solve the problem with the ethtool
interface.
Fixes: 06c16d89d2cb ("ice: register 1588 PTP clock device object for E810 devices")
Link: https://lore.kernel.org/netdev/20210804121318.337276-1-arnd@kernel.org/
Link: https://lore.kernel.org/netdev/CAK8P3a06enZOf=XyZ+zcAwBczv41UuCTz+=0FMf2gBz1_cOnZQ@mail.gmail.com/
Link: https://lore.kernel.org/netdev/CAK8P3a3=eOxE-K25754+fB_-i_0BZzf9a9RfPTX3ppSwu9WZXw@mail.gmail.com/
Link: https://lore.kernel.org/netdev/20210726084540.3282344-1-arnd@kernel.org/
Acked-by: Shannon Nelson <snelson@pensando.io>
Acked-by: Jacob Keller <jacob.e.keller@intel.com>
Acked-by: Richard Cochran <richardcochran@gmail.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210812183509.1362782-1-arnd@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-08-12 20:33:58 +02:00
|
|
|
depends on PTP_1588_CLOCK_OPTIONAL
|
2023-12-19 16:53:31 +02:00
|
|
|
depends on MACSEC || !MACSEC
|
2021-04-19 19:14:00 +03:00
|
|
|
help
|
|
|
|
Enable support for NXP C45 TJA11XX PHYs.
|
2025-02-28 17:43:20 +02:00
|
|
|
Currently supports the TJA1103, TJA1104, TJA1120 and TJA1121 PHYs.
|
2021-04-19 19:14:00 +03:00
|
|
|
|
2019-05-24 16:22:28 +02:00
|
|
|
config NXP_TJA11XX_PHY
|
|
|
|
tristate "NXP TJA11xx PHYs support"
|
|
|
|
depends on HWMON
|
2020-06-14 01:50:22 +09:00
|
|
|
help
|
2019-05-24 16:22:28 +02:00
|
|
|
Currently supports the NXP TJA1100 and TJA1101 PHY.
|
|
|
|
|
2023-01-09 18:00:38 +01:00
|
|
|
config NCN26000_PHY
|
|
|
|
tristate "Onsemi 10BASE-T1S Ethernet PHY"
|
|
|
|
help
|
|
|
|
Adds support for the onsemi 10BASE-T1S Ethernet PHY.
|
|
|
|
Currently supports the NCN26000 10BASE-T1S Industrial PHY
|
|
|
|
with MII interface.
|
|
|
|
|
2024-01-29 15:15:19 +01:00
|
|
|
source "drivers/net/phy/qcom/Kconfig"
|
2019-11-06 23:36:12 +01:00
|
|
|
|
2016-08-18 23:56:05 +02:00
|
|
|
config QSEMI_PHY
|
2016-08-18 23:56:06 +02:00
|
|
|
tristate "Quality Semiconductor PHYs"
|
2020-06-14 01:50:22 +09:00
|
|
|
help
|
2016-08-18 23:56:05 +02:00
|
|
|
Currently supports the qs6612
|
|
|
|
|
2025-01-11 21:50:19 +01:00
|
|
|
source "drivers/net/phy/realtek/Kconfig"
|
2016-08-18 23:56:05 +02:00
|
|
|
|
2017-10-08 13:40:08 +00:00
|
|
|
config RENESAS_PHY
|
2020-08-27 04:00:32 +02:00
|
|
|
tristate "Renesas PHYs"
|
2020-06-14 01:50:22 +09:00
|
|
|
help
|
2017-10-08 13:40:08 +00:00
|
|
|
Supports the Renesas PHYs uPD60620 and uPD60620A.
|
|
|
|
|
2017-08-10 21:56:40 +08:00
|
|
|
config ROCKCHIP_PHY
|
2020-08-27 04:00:32 +02:00
|
|
|
tristate "Rockchip Ethernet PHYs"
|
2020-06-14 01:50:22 +09:00
|
|
|
help
|
2019-09-23 17:52:43 +02:00
|
|
|
Currently supports the integrated Ethernet PHY.
|
2017-08-10 21:56:40 +08:00
|
|
|
|
2016-08-18 23:56:05 +02:00
|
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config SMSC_PHY
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2016-08-18 23:56:06 +02:00
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tristate "SMSC PHYs"
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2023-07-25 16:54:30 -07:00
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select CRC16
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2020-06-14 01:50:22 +09:00
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help
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2016-08-18 23:56:05 +02:00
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Currently supports the LAN83C185, LAN8187 and LAN8700 PHYs
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config STE10XP
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2016-08-18 23:56:06 +02:00
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tristate "STMicroelectronics STe10Xp PHYs"
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2020-06-14 01:50:22 +09:00
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help
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2016-08-18 23:56:05 +02:00
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This is the driver for the STe100p and STe101p PHYs.
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config TERANETICS_PHY
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2017-08-14 15:43:00 +02:00
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tristate "Teranetics PHYs"
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2020-06-14 01:50:22 +09:00
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help
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2017-08-14 15:43:00 +02:00
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Currently supports the Teranetics TN2020
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2016-08-18 23:56:05 +02:00
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2020-08-27 04:00:32 +02:00
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config DP83822_PHY
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tristate "Texas Instruments DP83822/825/826 PHYs"
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help
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Supports the DP83822, DP83825I, DP83825CM, DP83825CS, DP83825S,
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DP83826C and DP83826NC PHYs.
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config DP83TC811_PHY
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tristate "Texas Instruments DP83TC811 PHY"
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help
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Supports the DP83TC811 PHY.
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config DP83848_PHY
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tristate "Texas Instruments DP83848 PHY"
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help
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Supports the DP83848 PHY.
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config DP83867_PHY
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tristate "Texas Instruments DP83867 Gigabit PHY"
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help
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Currently supports the DP83867 PHY.
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config DP83869_PHY
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tristate "Texas Instruments DP83869 Gigabit PHY"
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help
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Currently supports the DP83869 PHY. This PHY supports copper and
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fiber connections.
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|
2022-05-06 06:23:57 +02:00
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config DP83TD510_PHY
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tristate "Texas Instruments DP83TD510 Ethernet 10Base-T1L PHY"
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help
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Support for the DP83TD510 Ethernet 10Base-T1L PHY. This PHY supports
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a 10M single pair Ethernet connection for up to 1000 meter cable.
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|
2023-12-12 06:41:44 +01:00
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config DP83TG720_PHY
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tristate "Texas Instruments DP83TG720 Ethernet 1000Base-T1 PHY"
|
2024-08-12 09:30:46 +02:00
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|
select OPEN_ALLIANCE_HELPERS
|
2023-12-12 06:41:44 +01:00
|
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help
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|
The DP83TG720S-Q1 is an automotive Ethernet physical layer
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|
transceiver compliant with IEEE 802.3bp and Open Alliance
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standards. It supports key functions necessary for
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transmitting and receiving data over both unshielded and
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shielded single twisted-pair cables. This device offers
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flexible xMII interface options, including support for both
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RGMII and SGMII MAC interfaces. It's suitable for applications
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|
|
requiring high-speed data transmission in automotive
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networking environments.
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|
2016-08-18 23:56:05 +02:00
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|
config VITESSE_PHY
|
2017-08-14 15:43:00 +02:00
|
|
|
tristate "Vitesse PHYs"
|
2020-06-14 01:50:22 +09:00
|
|
|
help
|
2017-08-14 15:43:00 +02:00
|
|
|
Currently supports the vsc8244
|
2016-08-18 23:56:05 +02:00
|
|
|
|
2016-08-10 11:20:08 +05:30
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|
|
config XILINX_GMII2RGMII
|
2017-08-14 15:43:00 +02:00
|
|
|
tristate "Xilinx GMII2RGMII converter driver"
|
2020-06-14 01:50:22 +09:00
|
|
|
help
|
2017-08-14 15:43:00 +02:00
|
|
|
This driver support xilinx GMII to RGMII IP core it provides
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|
|
|
the Reduced Gigabit Media Independent Interface(RGMII) between
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Ethernet physical media devices and the Gigabit Ethernet controller.
|
2016-08-10 11:20:08 +05:30
|
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|
|
2007-05-10 22:52:55 -07:00
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|
|
endif # PHYLIB
|
2011-12-18 07:33:41 +00:00
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config MICREL_KS8995MA
|
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|
|
tristate "Micrel KS8995MA 5-ports 10/100 managed Ethernet switch"
|
|
|
|
depends on SPI
|