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net: phy: add driver for MaxLinear MxL86110 PHY
Add support for the MaxLinear MxL86110 Gigabit Ethernet PHY, a low-power, cost-optimized transceiver supporting 10/100/1000 Mbps over twisted-pair copper, compliant with IEEE 802.3. The driver implements basic features such as: - Device initialization - RGMII interface timing configuration - Wake-on-LAN support - LED initialization and control via /sys/class/leds This driver has been tested on multiple Variscite boards, including: - VAR-SOM-MX93 (i.MX93) - VAR-SOM-MX8M-PLUS (i.MX8MP) Example boot log showing driver probe: [ 7.692101] imx-dwmac 428a0000.ethernet eth0: PHY [stmmac-0:00] driver [MXL86110 Gigabit Ethernet] (irq=POLL) Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250521212821.593057-1-stefano.radaelli21@gmail.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Stefano Radaelli
Paolo Abeni
parent
f484a3029a
commit
b2908a989c
4 changed files with 630 additions and 0 deletions
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@ -14675,6 +14675,7 @@ MAXLINEAR ETHERNET PHY DRIVER
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M: Xu Liang <lxu@maxlinear.com>
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L: netdev@vger.kernel.org
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S: Supported
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F: drivers/net/phy/mxl-86110.c
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F: drivers/net/phy/mxl-gpy.c
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MCAN MMIO DEVICE DRIVER
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@ -275,6 +275,18 @@ config MAXLINEAR_GPHY
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Support for the Maxlinear GPY115, GPY211, GPY212, GPY215,
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GPY241, GPY245 PHYs.
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config MAXLINEAR_86110_PHY
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tristate "MaxLinear MXL86110 PHY support"
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help
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Support for the MaxLinear MXL86110 Gigabit Ethernet
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Physical Layer transceiver.
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The MXL86110 is commonly used in networking equipment such as
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routers, switches, and embedded systems, providing the
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physical interface for 10/100/1000 Mbps Ethernet connections
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over copper media.
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If you are using a board with the MXL86110 PHY connected to your
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Ethernet MAC, you should enable this option.
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source "drivers/net/phy/mediatek/Kconfig"
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config MICREL_PHY
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@ -68,6 +68,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
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obj-$(CONFIG_MARVELL_88Q2XXX_PHY) += marvell-88q2xxx.o
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obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
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obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
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obj-$(CONFIG_MAXLINEAR_86110_PHY) += mxl-86110.o
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obj-y += mediatek/
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obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
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obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
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616
drivers/net/phy/mxl-86110.c
Normal file
616
drivers/net/phy/mxl-86110.c
Normal file
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@ -0,0 +1,616 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* PHY driver for Maxlinear MXL86110
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*
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* Copyright 2023 MaxLinear Inc.
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*
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*/
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#include <linux/bitfield.h>
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#include <linux/etherdevice.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy.h>
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/* PHY ID */
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#define PHY_ID_MXL86110 0xc1335580
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/* required to access extended registers */
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#define MXL86110_EXTD_REG_ADDR_OFFSET 0x1E
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#define MXL86110_EXTD_REG_ADDR_DATA 0x1F
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#define PHY_IRQ_ENABLE_REG 0x12
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#define PHY_IRQ_ENABLE_REG_WOL BIT(6)
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/* SyncE Configuration Register - COM_EXT SYNCE_CFG */
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#define MXL86110_EXT_SYNCE_CFG_REG 0xA012
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#define MXL86110_EXT_SYNCE_CFG_CLK_FRE_SEL BIT(4)
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#define MXL86110_EXT_SYNCE_CFG_EN_SYNC_E_DURING_LNKDN BIT(5)
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#define MXL86110_EXT_SYNCE_CFG_EN_SYNC_E BIT(6)
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#define MXL86110_EXT_SYNCE_CFG_CLK_SRC_SEL_MASK GENMASK(3, 1)
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#define MXL86110_EXT_SYNCE_CFG_CLK_SRC_SEL_125M_PLL 0
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#define MXL86110_EXT_SYNCE_CFG_CLK_SRC_SEL_25M 4
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/* MAC Address registers */
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#define MXL86110_EXT_MAC_ADDR_CFG1 0xA007
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#define MXL86110_EXT_MAC_ADDR_CFG2 0xA008
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#define MXL86110_EXT_MAC_ADDR_CFG3 0xA009
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#define MXL86110_EXT_WOL_CFG_REG 0xA00A
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#define MXL86110_WOL_CFG_WOL_MASK BIT(3)
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/* RGMII register */
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#define MXL86110_EXT_RGMII_CFG1_REG 0xA003
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/* delay can be adjusted in steps of about 150ps */
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#define MXL86110_EXT_RGMII_CFG1_RX_NO_DELAY (0x0 << 10)
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/* Closest value to 2000 ps */
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#define MXL86110_EXT_RGMII_CFG1_RX_DELAY_1950PS (0xD << 10)
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#define MXL86110_EXT_RGMII_CFG1_RX_DELAY_MASK GENMASK(13, 10)
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#define MXL86110_EXT_RGMII_CFG1_TX_1G_DELAY_1950PS (0xD << 0)
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#define MXL86110_EXT_RGMII_CFG1_TX_1G_DELAY_MASK GENMASK(3, 0)
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#define MXL86110_EXT_RGMII_CFG1_TX_10MB_100MB_DELAY_1950PS (0xD << 4)
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#define MXL86110_EXT_RGMII_CFG1_TX_10MB_100MB_DELAY_MASK GENMASK(7, 4)
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#define MXL86110_EXT_RGMII_CFG1_FULL_MASK \
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((MXL86110_EXT_RGMII_CFG1_RX_DELAY_MASK) | \
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(MXL86110_EXT_RGMII_CFG1_TX_1G_DELAY_MASK) | \
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(MXL86110_EXT_RGMII_CFG1_TX_10MB_100MB_DELAY_MASK))
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/* EXT Sleep Control register */
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#define MXL86110_UTP_EXT_SLEEP_CTRL_REG 0x27
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#define MXL86110_UTP_EXT_SLEEP_CTRL_EN_SLEEP_SW_OFF 0
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#define MXL86110_UTP_EXT_SLEEP_CTRL_EN_SLEEP_SW_MASK BIT(15)
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/* RGMII In-Band Status and MDIO Configuration Register */
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#define MXL86110_EXT_RGMII_MDIO_CFG 0xA005
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#define MXL86110_RGMII_MDIO_CFG_EPA0_MASK GENMASK(6, 6)
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#define MXL86110_EXT_RGMII_MDIO_CFG_EBA_MASK GENMASK(5, 5)
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#define MXL86110_EXT_RGMII_MDIO_CFG_BA_MASK GENMASK(4, 0)
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#define MXL86110_MAX_LEDS 3
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/* LED registers and defines */
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#define MXL86110_LED0_CFG_REG 0xA00C
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#define MXL86110_LED1_CFG_REG 0xA00D
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#define MXL86110_LED2_CFG_REG 0xA00E
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#define MXL86110_LEDX_CFG_BLINK BIT(13)
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#define MXL86110_LEDX_CFG_LINK_UP_FULL_DUPLEX_ON BIT(12)
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#define MXL86110_LEDX_CFG_LINK_UP_HALF_DUPLEX_ON BIT(11)
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#define MXL86110_LEDX_CFG_LINK_UP_TX_ACT_ON BIT(10)
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#define MXL86110_LEDX_CFG_LINK_UP_RX_ACT_ON BIT(9)
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#define MXL86110_LEDX_CFG_LINK_UP_TX_ON BIT(8)
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#define MXL86110_LEDX_CFG_LINK_UP_RX_ON BIT(7)
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#define MXL86110_LEDX_CFG_LINK_UP_1GB_ON BIT(6)
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#define MXL86110_LEDX_CFG_LINK_UP_100MB_ON BIT(5)
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#define MXL86110_LEDX_CFG_LINK_UP_10MB_ON BIT(4)
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#define MXL86110_LEDX_CFG_LINK_UP_COLLISION BIT(3)
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#define MXL86110_LEDX_CFG_LINK_UP_1GB_BLINK BIT(2)
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#define MXL86110_LEDX_CFG_LINK_UP_100MB_BLINK BIT(1)
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#define MXL86110_LEDX_CFG_LINK_UP_10MB_BLINK BIT(0)
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#define MXL86110_LED_BLINK_CFG_REG 0xA00F
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#define MXL86110_LED_BLINK_CFG_FREQ_MODE1_2HZ 0
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#define MXL86110_LED_BLINK_CFG_FREQ_MODE1_4HZ BIT(0)
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#define MXL86110_LED_BLINK_CFG_FREQ_MODE1_8HZ BIT(1)
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#define MXL86110_LED_BLINK_CFG_FREQ_MODE1_16HZ (BIT(1) | BIT(0))
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#define MXL86110_LED_BLINK_CFG_FREQ_MODE2_2HZ 0
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#define MXL86110_LED_BLINK_CFG_FREQ_MODE2_4HZ BIT(2)
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#define MXL86110_LED_BLINK_CFG_FREQ_MODE2_8HZ BIT(3)
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#define MXL86110_LED_BLINK_CFG_FREQ_MODE2_16HZ (BIT(3) | BIT(2))
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#define MXL86110_LED_BLINK_CFG_DUTY_CYCLE_50_ON 0
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#define MXL86110_LED_BLINK_CFG_DUTY_CYCLE_67_ON (BIT(4))
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#define MXL86110_LED_BLINK_CFG_DUTY_CYCLE_75_ON (BIT(5))
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#define MXL86110_LED_BLINK_CFG_DUTY_CYCLE_83_ON (BIT(5) | BIT(4))
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#define MXL86110_LED_BLINK_CFG_DUTY_CYCLE_50_OFF (BIT(6))
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#define MXL86110_LED_BLINK_CFG_DUTY_CYCLE_33_ON (BIT(6) | BIT(4))
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#define MXL86110_LED_BLINK_CFG_DUTY_CYCLE_25_ON (BIT(6) | BIT(5))
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#define MXL86110_LED_BLINK_CFG_DUTY_CYCLE_17_ON (BIT(6) | BIT(5) | BIT(4))
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/* Chip Configuration Register - COM_EXT_CHIP_CFG */
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#define MXL86110_EXT_CHIP_CFG_REG 0xA001
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#define MXL86110_EXT_CHIP_CFG_RXDLY_ENABLE BIT(8)
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#define MXL86110_EXT_CHIP_CFG_SW_RST_N_MODE BIT(15)
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/**
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* __mxl86110_write_extended_reg() - write to a PHY's extended register
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* @phydev: pointer to the PHY device structure
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* @regnum: register number to write
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* @val: value to write to @regnum
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*
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* Unlocked version of mxl86110_write_extended_reg
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*
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* Note: This function assumes the caller already holds the MDIO bus lock
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* or otherwise has exclusive access to the PHY.
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*
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* Return: 0 or negative error code
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*/
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static int __mxl86110_write_extended_reg(struct phy_device *phydev,
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u16 regnum, u16 val)
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{
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int ret;
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ret = __phy_write(phydev, MXL86110_EXTD_REG_ADDR_OFFSET, regnum);
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if (ret < 0)
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return ret;
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return __phy_write(phydev, MXL86110_EXTD_REG_ADDR_DATA, val);
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}
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/**
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* __mxl86110_read_extended_reg - Read a PHY's extended register
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* @phydev: pointer to the PHY device structure
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* @regnum: extended register number to read (address written to reg 30)
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*
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* Unlocked version of mxl86110_read_extended_reg
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*
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* Reads the content of a PHY extended register using the MaxLinear
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* 2-step access mechanism: write the register address to reg 30 (0x1E),
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* then read the value from reg 31 (0x1F).
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*
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* Note: This function assumes the caller already holds the MDIO bus lock
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* or otherwise has exclusive access to the PHY.
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*
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* Return: 16-bit register value on success, or negative errno code on failure.
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*/
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static int __mxl86110_read_extended_reg(struct phy_device *phydev, u16 regnum)
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{
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int ret;
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ret = __phy_write(phydev, MXL86110_EXTD_REG_ADDR_OFFSET, regnum);
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if (ret < 0)
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return ret;
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return __phy_read(phydev, MXL86110_EXTD_REG_ADDR_DATA);
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}
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/**
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* __mxl86110_modify_extended_reg() - modify bits of a PHY's extended register
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* @phydev: pointer to the PHY device structure
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* @regnum: register number to write
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* @mask: bit mask of bits to clear
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* @set: bit mask of bits to set
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*
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* Note: register value = (old register value & ~mask) | set.
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* This function assumes the caller already holds the MDIO bus lock
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* or otherwise has exclusive access to the PHY.
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*
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* Return: 0 or negative error code
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*/
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static int __mxl86110_modify_extended_reg(struct phy_device *phydev,
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u16 regnum, u16 mask, u16 set)
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{
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int ret;
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ret = __phy_write(phydev, MXL86110_EXTD_REG_ADDR_OFFSET, regnum);
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if (ret < 0)
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return ret;
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return __phy_modify(phydev, MXL86110_EXTD_REG_ADDR_DATA, mask, set);
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}
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/**
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* mxl86110_write_extended_reg() - Write to a PHY's extended register
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* @phydev: pointer to the PHY device structure
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* @regnum: register number to write
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* @val: value to write to @regnum
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*
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* This function writes to an extended register of the PHY using the
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* MaxLinear two-step access method (reg 0x1E/0x1F). It handles acquiring
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* and releasing the MDIO bus lock internally.
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*
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* Return: 0 or negative error code
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*/
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static int mxl86110_write_extended_reg(struct phy_device *phydev,
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u16 regnum, u16 val)
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{
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int ret;
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phy_lock_mdio_bus(phydev);
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ret = __mxl86110_write_extended_reg(phydev, regnum, val);
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phy_unlock_mdio_bus(phydev);
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return ret;
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}
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/**
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* mxl86110_read_extended_reg() - Read a PHY's extended register
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* @phydev: pointer to the PHY device structure
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* @regnum: extended register number to read
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*
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* This function reads from an extended register of the PHY using the
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* MaxLinear two-step access method (reg 0x1E/0x1F). It handles acquiring
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* and releasing the MDIO bus lock internally.
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*
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* Return: 16-bit register value on success, or negative errno code on failure
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*/
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static int mxl86110_read_extended_reg(struct phy_device *phydev, u16 regnum)
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{
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int ret;
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phy_lock_mdio_bus(phydev);
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ret = __mxl86110_read_extended_reg(phydev, regnum);
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phy_unlock_mdio_bus(phydev);
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return ret;
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}
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/**
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* mxl86110_get_wol() - report if wake-on-lan is enabled
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* @phydev: pointer to the phy_device
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* @wol: a pointer to a &struct ethtool_wolinfo
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*/
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static void mxl86110_get_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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int val;
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wol->supported = WAKE_MAGIC;
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wol->wolopts = 0;
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val = mxl86110_read_extended_reg(phydev, MXL86110_EXT_WOL_CFG_REG);
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if (val >= 0 && (val & MXL86110_WOL_CFG_WOL_MASK))
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wol->wolopts |= WAKE_MAGIC;
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}
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/**
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* mxl86110_set_wol() - enable/disable wake-on-lan
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* @phydev: pointer to the phy_device
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* @wol: a pointer to a &struct ethtool_wolinfo
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*
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* Configures the WOL Magic Packet MAC
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*
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* Return: 0 or negative errno code
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*/
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static int mxl86110_set_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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struct net_device *netdev;
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const unsigned char *mac;
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int ret = 0;
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phy_lock_mdio_bus(phydev);
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if (wol->wolopts & WAKE_MAGIC) {
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netdev = phydev->attached_dev;
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if (!netdev) {
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ret = -ENODEV;
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goto out;
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}
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/* Configure the MAC address of the WOL magic packet */
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mac = netdev->dev_addr;
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ret = __mxl86110_write_extended_reg(phydev,
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MXL86110_EXT_MAC_ADDR_CFG1,
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((mac[0] << 8) | mac[1]));
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if (ret < 0)
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goto out;
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ret = __mxl86110_write_extended_reg(phydev,
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MXL86110_EXT_MAC_ADDR_CFG2,
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((mac[2] << 8) | mac[3]));
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if (ret < 0)
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goto out;
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ret = __mxl86110_write_extended_reg(phydev,
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MXL86110_EXT_MAC_ADDR_CFG3,
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((mac[4] << 8) | mac[5]));
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if (ret < 0)
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goto out;
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ret = __mxl86110_modify_extended_reg(phydev,
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MXL86110_EXT_WOL_CFG_REG,
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MXL86110_WOL_CFG_WOL_MASK,
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MXL86110_WOL_CFG_WOL_MASK);
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if (ret < 0)
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goto out;
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/* Enables Wake-on-LAN interrupt in the PHY. */
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ret = __phy_modify(phydev, PHY_IRQ_ENABLE_REG, 0,
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PHY_IRQ_ENABLE_REG_WOL);
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if (ret < 0)
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goto out;
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phydev_dbg(phydev,
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"%s, MAC Addr: %02X:%02X:%02X:%02X:%02X:%02X\n",
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__func__,
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mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
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} else {
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ret = __mxl86110_modify_extended_reg(phydev,
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MXL86110_EXT_WOL_CFG_REG,
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MXL86110_WOL_CFG_WOL_MASK,
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0);
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if (ret < 0)
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goto out;
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/* Disables Wake-on-LAN interrupt in the PHY. */
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ret = __phy_modify(phydev, PHY_IRQ_ENABLE_REG,
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PHY_IRQ_ENABLE_REG_WOL, 0);
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}
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out:
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phy_unlock_mdio_bus(phydev);
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return ret;
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}
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|
||||
static const unsigned long supported_trgs = (BIT(TRIGGER_NETDEV_LINK_10) |
|
||||
BIT(TRIGGER_NETDEV_LINK_100) |
|
||||
BIT(TRIGGER_NETDEV_LINK_1000) |
|
||||
BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
|
||||
BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
|
||||
BIT(TRIGGER_NETDEV_TX) |
|
||||
BIT(TRIGGER_NETDEV_RX));
|
||||
|
||||
static int mxl86110_led_hw_is_supported(struct phy_device *phydev, u8 index,
|
||||
unsigned long rules)
|
||||
{
|
||||
if (index >= MXL86110_MAX_LEDS)
|
||||
return -EINVAL;
|
||||
|
||||
/* All combinations of the supported triggers are allowed */
|
||||
if (rules & ~supported_trgs)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mxl86110_led_hw_control_get(struct phy_device *phydev, u8 index,
|
||||
unsigned long *rules)
|
||||
{
|
||||
int val;
|
||||
|
||||
if (index >= MXL86110_MAX_LEDS)
|
||||
return -EINVAL;
|
||||
|
||||
val = mxl86110_read_extended_reg(phydev,
|
||||
MXL86110_LED0_CFG_REG + index);
|
||||
if (val < 0)
|
||||
return val;
|
||||
|
||||
if (val & MXL86110_LEDX_CFG_LINK_UP_TX_ACT_ON)
|
||||
*rules |= BIT(TRIGGER_NETDEV_TX);
|
||||
|
||||
if (val & MXL86110_LEDX_CFG_LINK_UP_RX_ACT_ON)
|
||||
*rules |= BIT(TRIGGER_NETDEV_RX);
|
||||
|
||||
if (val & MXL86110_LEDX_CFG_LINK_UP_HALF_DUPLEX_ON)
|
||||
*rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
|
||||
|
||||
if (val & MXL86110_LEDX_CFG_LINK_UP_FULL_DUPLEX_ON)
|
||||
*rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
|
||||
|
||||
if (val & MXL86110_LEDX_CFG_LINK_UP_10MB_ON)
|
||||
*rules |= BIT(TRIGGER_NETDEV_LINK_10);
|
||||
|
||||
if (val & MXL86110_LEDX_CFG_LINK_UP_100MB_ON)
|
||||
*rules |= BIT(TRIGGER_NETDEV_LINK_100);
|
||||
|
||||
if (val & MXL86110_LEDX_CFG_LINK_UP_1GB_ON)
|
||||
*rules |= BIT(TRIGGER_NETDEV_LINK_1000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mxl86110_led_hw_control_set(struct phy_device *phydev, u8 index,
|
||||
unsigned long rules)
|
||||
{
|
||||
u16 val = 0;
|
||||
|
||||
if (index >= MXL86110_MAX_LEDS)
|
||||
return -EINVAL;
|
||||
|
||||
if (rules & BIT(TRIGGER_NETDEV_LINK_10))
|
||||
val |= MXL86110_LEDX_CFG_LINK_UP_10MB_ON;
|
||||
|
||||
if (rules & BIT(TRIGGER_NETDEV_LINK_100))
|
||||
val |= MXL86110_LEDX_CFG_LINK_UP_100MB_ON;
|
||||
|
||||
if (rules & BIT(TRIGGER_NETDEV_LINK_1000))
|
||||
val |= MXL86110_LEDX_CFG_LINK_UP_1GB_ON;
|
||||
|
||||
if (rules & BIT(TRIGGER_NETDEV_TX))
|
||||
val |= MXL86110_LEDX_CFG_LINK_UP_TX_ACT_ON;
|
||||
|
||||
if (rules & BIT(TRIGGER_NETDEV_RX))
|
||||
val |= MXL86110_LEDX_CFG_LINK_UP_RX_ACT_ON;
|
||||
|
||||
if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
|
||||
val |= MXL86110_LEDX_CFG_LINK_UP_HALF_DUPLEX_ON;
|
||||
|
||||
if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
|
||||
val |= MXL86110_LEDX_CFG_LINK_UP_FULL_DUPLEX_ON;
|
||||
|
||||
if (rules & BIT(TRIGGER_NETDEV_TX) ||
|
||||
rules & BIT(TRIGGER_NETDEV_RX))
|
||||
val |= MXL86110_LEDX_CFG_BLINK;
|
||||
|
||||
return mxl86110_write_extended_reg(phydev,
|
||||
MXL86110_LED0_CFG_REG + index, val);
|
||||
}
|
||||
|
||||
/**
|
||||
* mxl86110_synce_clk_cfg() - applies syncE/clk output configuration
|
||||
* @phydev: pointer to the phy_device
|
||||
*
|
||||
* Note: This function assumes the caller already holds the MDIO bus lock
|
||||
* or otherwise has exclusive access to the PHY.
|
||||
*
|
||||
* Return: 0 or negative errno code
|
||||
*/
|
||||
static int mxl86110_synce_clk_cfg(struct phy_device *phydev)
|
||||
{
|
||||
u16 mask = 0, val = 0;
|
||||
|
||||
/*
|
||||
* Configures the clock output to its default
|
||||
* setting as per the datasheet.
|
||||
* This results in a 25MHz clock output being selected in the
|
||||
* COM_EXT_SYNCE_CFG register for SyncE configuration.
|
||||
*/
|
||||
val = MXL86110_EXT_SYNCE_CFG_EN_SYNC_E |
|
||||
FIELD_PREP(MXL86110_EXT_SYNCE_CFG_CLK_SRC_SEL_MASK,
|
||||
MXL86110_EXT_SYNCE_CFG_CLK_SRC_SEL_25M);
|
||||
mask = MXL86110_EXT_SYNCE_CFG_EN_SYNC_E |
|
||||
MXL86110_EXT_SYNCE_CFG_CLK_SRC_SEL_MASK |
|
||||
MXL86110_EXT_SYNCE_CFG_CLK_FRE_SEL;
|
||||
|
||||
/* Write clock output configuration */
|
||||
return __mxl86110_modify_extended_reg(phydev,
|
||||
MXL86110_EXT_SYNCE_CFG_REG,
|
||||
mask, val);
|
||||
}
|
||||
|
||||
/**
|
||||
* mxl86110_broadcast_cfg - Configure MDIO broadcast setting for PHY
|
||||
* @phydev: Pointer to the PHY device structure
|
||||
*
|
||||
* This function configures the MDIO broadcast behavior of the MxL86110 PHY.
|
||||
* Currently, broadcast mode is explicitly disabled by clearing the EPA0 bit
|
||||
* in the RGMII_MDIO_CFG extended register.
|
||||
*
|
||||
* Note: This function assumes the caller already holds the MDIO bus lock
|
||||
* or otherwise has exclusive access to the PHY.
|
||||
*
|
||||
* Return: 0 on success or a negative errno code on failure.
|
||||
*/
|
||||
static int mxl86110_broadcast_cfg(struct phy_device *phydev)
|
||||
{
|
||||
return __mxl86110_modify_extended_reg(phydev,
|
||||
MXL86110_EXT_RGMII_MDIO_CFG,
|
||||
MXL86110_RGMII_MDIO_CFG_EPA0_MASK,
|
||||
0);
|
||||
}
|
||||
|
||||
/**
|
||||
* mxl86110_enable_led_activity_blink - Enable LEDs activity blink on PHY
|
||||
* @phydev: Pointer to the PHY device structure
|
||||
*
|
||||
* Configure all PHY LEDs to blink on traffic activity regardless of whether
|
||||
* they are ON or OFF. This behavior allows each LED to serve as a pure activity
|
||||
* indicator, independently of its use as a link status indicator.
|
||||
*
|
||||
* By default, each LED blinks only when it is also in the ON state.
|
||||
* This function modifies the appropriate registers (LABx fields)
|
||||
* to enable blinking even when the LEDs are OFF, to allow the LED to be used
|
||||
* as a traffic indicator without requiring it to also serve
|
||||
* as a link status LED.
|
||||
*
|
||||
* Note: Any further LED customization can be performed via the
|
||||
* /sys/class/leds interface; the functions led_hw_is_supported,
|
||||
* led_hw_control_get, and led_hw_control_set are used
|
||||
* to support this mechanism.
|
||||
*
|
||||
* This function assumes the caller already holds the MDIO bus lock
|
||||
* or otherwise has exclusive access to the PHY.
|
||||
*
|
||||
* Return: 0 on success or a negative errno code on failure.
|
||||
*/
|
||||
static int mxl86110_enable_led_activity_blink(struct phy_device *phydev)
|
||||
{
|
||||
int i, ret = 0;
|
||||
|
||||
for (i = 0; i < MXL86110_MAX_LEDS; i++) {
|
||||
ret = __mxl86110_modify_extended_reg(phydev,
|
||||
MXL86110_LED0_CFG_REG + i,
|
||||
0,
|
||||
MXL86110_LEDX_CFG_BLINK);
|
||||
if (ret < 0)
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* mxl86110_config_init() - initialize the PHY
|
||||
* @phydev: pointer to the phy_device
|
||||
*
|
||||
* Return: 0 or negative errno code
|
||||
*/
|
||||
static int mxl86110_config_init(struct phy_device *phydev)
|
||||
{
|
||||
u16 val = 0;
|
||||
int ret;
|
||||
|
||||
phy_lock_mdio_bus(phydev);
|
||||
|
||||
/* configure syncE / clk output */
|
||||
ret = mxl86110_synce_clk_cfg(phydev);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
switch (phydev->interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
val = 0;
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||
val = MXL86110_EXT_RGMII_CFG1_RX_DELAY_1950PS;
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||
val = MXL86110_EXT_RGMII_CFG1_TX_1G_DELAY_1950PS |
|
||||
MXL86110_EXT_RGMII_CFG1_TX_10MB_100MB_DELAY_1950PS;
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||
val = MXL86110_EXT_RGMII_CFG1_TX_1G_DELAY_1950PS |
|
||||
MXL86110_EXT_RGMII_CFG1_TX_10MB_100MB_DELAY_1950PS |
|
||||
MXL86110_EXT_RGMII_CFG1_RX_DELAY_1950PS;
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = __mxl86110_modify_extended_reg(phydev,
|
||||
MXL86110_EXT_RGMII_CFG1_REG,
|
||||
MXL86110_EXT_RGMII_CFG1_FULL_MASK,
|
||||
val);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
/* Configure RXDLY (RGMII Rx Clock Delay) to disable
|
||||
* the default additional delay value on RX_CLK
|
||||
* (2 ns for 125 MHz, 8 ns for 25 MHz/2.5 MHz)
|
||||
* and use just the digital one selected before
|
||||
*/
|
||||
ret = __mxl86110_modify_extended_reg(phydev,
|
||||
MXL86110_EXT_CHIP_CFG_REG,
|
||||
MXL86110_EXT_CHIP_CFG_RXDLY_ENABLE,
|
||||
0);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
ret = mxl86110_enable_led_activity_blink(phydev);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
ret = mxl86110_broadcast_cfg(phydev);
|
||||
|
||||
out:
|
||||
phy_unlock_mdio_bus(phydev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct phy_driver mxl_phy_drvs[] = {
|
||||
{
|
||||
PHY_ID_MATCH_EXACT(PHY_ID_MXL86110),
|
||||
.name = "MXL86110 Gigabit Ethernet",
|
||||
.config_init = mxl86110_config_init,
|
||||
.get_wol = mxl86110_get_wol,
|
||||
.set_wol = mxl86110_set_wol,
|
||||
.led_hw_is_supported = mxl86110_led_hw_is_supported,
|
||||
.led_hw_control_get = mxl86110_led_hw_control_get,
|
||||
.led_hw_control_set = mxl86110_led_hw_control_set,
|
||||
},
|
||||
};
|
||||
|
||||
module_phy_driver(mxl_phy_drvs);
|
||||
|
||||
static const struct mdio_device_id __maybe_unused mxl_tbl[] = {
|
||||
{ PHY_ID_MATCH_EXACT(PHY_ID_MXL86110) },
|
||||
{ }
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(mdio, mxl_tbl);
|
||||
|
||||
MODULE_DESCRIPTION("MaxLinear MXL86110 PHY driver");
|
||||
MODULE_AUTHOR("Stefano Radaelli");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Add table
Reference in a new issue