2022-11-08 23:01:20 +05:30
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 Radxa Limited
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* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
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*
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* Author:
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* - Jagan Teki <jagan@amarulasolutions.com>
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* - Stephen Chen <stephen@radxa.com>
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*/
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_modes.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_print.h>
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#include <linux/gpio/consumer.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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2023-07-14 11:45:34 -06:00
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#include <linux/of.h>
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2022-11-08 23:01:20 +05:30
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#include <linux/regulator/consumer.h>
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2024-06-24 22:19:24 +08:00
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struct jadard;
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2022-11-08 23:01:20 +05:30
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struct jadard_panel_desc {
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const struct drm_display_mode mode;
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unsigned int lanes;
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enum mipi_dsi_pixel_format format;
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2024-06-24 22:19:24 +08:00
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int (*init)(struct jadard *jadard);
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2024-06-24 22:19:25 +08:00
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bool lp11_before_reset;
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bool reset_before_power_off_vcioo;
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unsigned int vcioo_to_lp11_delay_ms;
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unsigned int lp11_to_reset_delay_ms;
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unsigned int backlight_off_to_display_off_delay_ms;
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unsigned int display_off_to_enter_sleep_delay_ms;
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unsigned int enter_sleep_to_reset_down_delay_ms;
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2022-11-08 23:01:20 +05:30
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};
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struct jadard {
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struct drm_panel panel;
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struct mipi_dsi_device *dsi;
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const struct jadard_panel_desc *desc;
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2024-06-24 22:19:26 +08:00
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enum drm_panel_orientation orientation;
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2022-11-08 23:01:20 +05:30
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struct regulator *vdd;
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struct regulator *vccio;
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struct gpio_desc *reset;
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};
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2024-07-04 12:50:17 +08:00
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#define JD9365DA_DCS_SWITCH_PAGE 0xe0
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#define jd9365da_switch_page(dsi_ctx, page) \
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, JD9365DA_DCS_SWITCH_PAGE, (page))
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static void jadard_enable_standard_cmds(struct mipi_dsi_multi_context *dsi_ctx)
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{
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe1, 0x93);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe2, 0x65);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe3, 0xf8);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x03);
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}
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2022-11-08 23:01:20 +05:30
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static inline struct jadard *panel_to_jadard(struct drm_panel *panel)
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{
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return container_of(panel, struct jadard, panel);
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}
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static int jadard_disable(struct drm_panel *panel)
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{
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struct jadard *jadard = panel_to_jadard(panel);
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2024-06-24 22:19:24 +08:00
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struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
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2022-11-08 23:01:20 +05:30
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2024-06-24 22:19:25 +08:00
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if (jadard->desc->backlight_off_to_display_off_delay_ms)
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mipi_dsi_msleep(&dsi_ctx, jadard->desc->backlight_off_to_display_off_delay_ms);
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2024-06-24 22:19:24 +08:00
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mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
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2022-11-08 23:01:20 +05:30
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2024-06-24 22:19:25 +08:00
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if (jadard->desc->display_off_to_enter_sleep_delay_ms)
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mipi_dsi_msleep(&dsi_ctx, jadard->desc->display_off_to_enter_sleep_delay_ms);
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2024-06-24 22:19:24 +08:00
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mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
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2022-11-08 23:01:20 +05:30
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2024-06-24 22:19:25 +08:00
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if (jadard->desc->enter_sleep_to_reset_down_delay_ms)
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mipi_dsi_msleep(&dsi_ctx, jadard->desc->enter_sleep_to_reset_down_delay_ms);
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2024-06-24 22:19:24 +08:00
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return dsi_ctx.accum_err;
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2022-11-08 23:01:20 +05:30
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}
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static int jadard_prepare(struct drm_panel *panel)
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{
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struct jadard *jadard = panel_to_jadard(panel);
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int ret;
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ret = regulator_enable(jadard->vccio);
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if (ret)
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return ret;
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ret = regulator_enable(jadard->vdd);
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if (ret)
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return ret;
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2024-06-24 22:19:25 +08:00
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if (jadard->desc->vcioo_to_lp11_delay_ms)
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msleep(jadard->desc->vcioo_to_lp11_delay_ms);
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if (jadard->desc->lp11_before_reset) {
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ret = mipi_dsi_dcs_nop(jadard->dsi);
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if (ret)
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return ret;
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}
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if (jadard->desc->lp11_to_reset_delay_ms)
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msleep(jadard->desc->lp11_to_reset_delay_ms);
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2024-09-27 09:53:05 -04:00
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gpiod_set_value(jadard->reset, 0);
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2022-11-08 23:01:20 +05:30
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msleep(5);
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2024-09-27 09:53:05 -04:00
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gpiod_set_value(jadard->reset, 1);
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2022-11-08 23:01:20 +05:30
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msleep(10);
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2024-09-27 09:53:05 -04:00
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gpiod_set_value(jadard->reset, 0);
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2024-06-24 22:19:22 +08:00
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msleep(130);
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2024-06-24 22:19:24 +08:00
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ret = jadard->desc->init(jadard);
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if (ret)
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return ret;
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2022-11-08 23:01:20 +05:30
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return 0;
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}
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static int jadard_unprepare(struct drm_panel *panel)
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{
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struct jadard *jadard = panel_to_jadard(panel);
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2025-04-17 15:55:06 -04:00
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gpiod_set_value(jadard->reset, 0);
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2022-11-08 23:01:20 +05:30
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msleep(120);
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2024-06-24 22:19:25 +08:00
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if (jadard->desc->reset_before_power_off_vcioo) {
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2025-04-17 15:55:06 -04:00
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gpiod_set_value(jadard->reset, 1);
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2024-06-24 22:19:25 +08:00
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usleep_range(1000, 2000);
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}
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2022-11-08 23:01:20 +05:30
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regulator_disable(jadard->vdd);
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regulator_disable(jadard->vccio);
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return 0;
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}
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static int jadard_get_modes(struct drm_panel *panel,
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struct drm_connector *connector)
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{
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struct jadard *jadard = panel_to_jadard(panel);
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const struct drm_display_mode *desc_mode = &jadard->desc->mode;
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struct drm_display_mode *mode;
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mode = drm_mode_duplicate(connector->dev, desc_mode);
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if (!mode) {
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DRM_DEV_ERROR(&jadard->dsi->dev, "failed to add mode %ux%ux@%u\n",
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desc_mode->hdisplay, desc_mode->vdisplay,
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drm_mode_vrefresh(desc_mode));
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return -ENOMEM;
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}
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drm_mode_set_name(mode);
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drm_mode_probed_add(connector, mode);
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connector->display_info.width_mm = mode->width_mm;
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connector->display_info.height_mm = mode->height_mm;
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return 1;
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}
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2024-06-24 22:19:26 +08:00
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static enum drm_panel_orientation jadard_panel_get_orientation(struct drm_panel *panel)
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{
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struct jadard *jadard = panel_to_jadard(panel);
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return jadard->orientation;
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}
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2022-11-08 23:01:20 +05:30
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static const struct drm_panel_funcs jadard_funcs = {
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.disable = jadard_disable,
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.unprepare = jadard_unprepare,
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.prepare = jadard_prepare,
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.get_modes = jadard_get_modes,
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2024-06-24 22:19:26 +08:00
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.get_orientation = jadard_panel_get_orientation,
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2022-11-08 23:01:20 +05:30
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};
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2024-06-24 22:19:24 +08:00
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static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard)
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{
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struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
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2024-07-04 12:50:17 +08:00
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jd9365da_switch_page(&dsi_ctx, 0x00);
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jadard_enable_standard_cmds(&dsi_ctx);
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jd9365da_switch_page(&dsi_ctx, 0x01);
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2024-06-24 22:19:24 +08:00
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7E);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xB7);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xB7);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xFE);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x70);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0xFF);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1E);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0F);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x04);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xA9);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0A);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x37);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x19);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x78);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x63);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x54);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x49);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3D);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x57);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x49);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x44);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x37);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x23);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x10);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3D);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x62);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x50);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x57);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x49);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x44);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10);
|
2024-07-04 12:50:17 +08:00
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x02);
|
2024-06-24 22:19:24 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4B);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4B);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x5F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x4A);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x4A);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x48);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x48);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x40);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x10);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x06);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x40);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x01);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6B);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0C);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x56);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x04);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x04);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7B);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xF8);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xD5);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2E);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x03);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x03);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x7B);
|
2024-07-04 12:50:17 +08:00
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x04);
|
2024-06-24 22:19:24 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x2A);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59);
|
2024-07-04 12:50:17 +08:00
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x00);
|
2024-06-24 22:19:24 +08:00
|
|
|
|
drm/panel: jd9365da: Move "exit sleep mode" and "set display on" cmds
Move the "exit sleep mode" and "set display on" command from
enable() to init() function.
As mentioned in the patch:
https://lore.kernel.org/all/20240624141926.5250-2-lvzhaoxiong@huaqin.corp-partner.google.com/
The Mediatek Soc DSI host has different modes in prepare() and
enable() functions, prepare() is in LP mode and enable() is in
HS mode. Since the "exit sleep mode" and "set display on"
command must also be sent in LP mode, so we also move "exit
sleep mode" and "set display on" command to the init() function.
We have no other actions in the enable() function after moves
"exit sleep mode" and "set display on", and we checked the call
of the enable() function during the "startup" process. It seems
that only one judgment was made in drm_panel_enabel(). If the
panel does not define enable(), the judgment will skip the
enable() and continue execution. This does not seem to have
any other effect, and we found that some drivers also seem
to have no enable() function added, for example:
panel-asus-z00t-tm5p5-n35596 / panel-boe-himax8279d...
In addition, we briefly tested the kingdisplay_kd101ne3 panel and
melfas_lmfbx101117480 panel, and it seems that there is no garbage
on the panel, so we delete enable() function.
After moving the "exit sleep mode" and "set display on" command
to the init() function, we no longer need additional delay
judgment, so we delete variables "exit_sleep_to_display_on_delay_ms"
and "display_on_delay_ms".
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com>
Acked-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Link: https://lore.kernel.org/r/20240807100429.13260-2-lvzhaoxiong@huaqin.corp-partner.google.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240807100429.13260-2-lvzhaoxiong@huaqin.corp-partner.google.com
2024-08-07 18:04:28 +08:00
|
|
|
mipi_dsi_msleep(&dsi_ctx, 120);
|
|
|
|
|
|
|
|
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
|
|
|
|
|
|
|
|
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
|
|
|
|
|
2024-06-24 22:19:24 +08:00
|
|
|
return dsi_ctx.accum_err;
|
2023-01-24 00:03:12 +05:30
|
|
|
};
|
|
|
|
|
|
|
|
static const struct jadard_panel_desc radxa_display_8hd_ad002_desc = {
|
|
|
|
.mode = {
|
|
|
|
.clock = 70000,
|
|
|
|
|
|
|
|
.hdisplay = 800,
|
|
|
|
.hsync_start = 800 + 40,
|
|
|
|
.hsync_end = 800 + 40 + 18,
|
|
|
|
.htotal = 800 + 40 + 18 + 20,
|
|
|
|
|
|
|
|
.vdisplay = 1280,
|
|
|
|
.vsync_start = 1280 + 20,
|
|
|
|
.vsync_end = 1280 + 20 + 4,
|
|
|
|
.vtotal = 1280 + 20 + 4 + 20,
|
|
|
|
|
|
|
|
.width_mm = 127,
|
|
|
|
.height_mm = 199,
|
|
|
|
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
|
|
|
|
},
|
|
|
|
.lanes = 4,
|
|
|
|
.format = MIPI_DSI_FMT_RGB888,
|
2024-06-24 22:19:24 +08:00
|
|
|
.init = radxa_display_8hd_ad002_init_cmds,
|
2023-01-24 00:03:12 +05:30
|
|
|
};
|
|
|
|
|
2024-06-24 22:19:24 +08:00
|
|
|
static int cz101b4001_init_cmds(struct jadard *jadard)
|
|
|
|
{
|
|
|
|
struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
|
|
|
|
|
2024-07-04 12:50:17 +08:00
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x00);
|
|
|
|
jadard_enable_standard_cmds(&dsi_ctx);
|
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x01);
|
2024-06-24 22:19:24 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3B);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xAF);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xAF);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x78);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x7F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x81);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x14);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x23);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x69);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x2A);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x7F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x6B);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x5C);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4D);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x42);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2B);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x44);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x43);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x63);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x52);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x5A);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x4F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x4E);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x20);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x0F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6B);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5C);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4D);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x42);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2B);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x44);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x43);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x63);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x52);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x5A);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x4F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x4E);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00);
|
2024-07-04 12:50:17 +08:00
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x02);
|
2024-06-24 22:19:24 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x1E);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x1E);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x37);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x37);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x47);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x47);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x45);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x45);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4B);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x4B);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x49);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x49);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x01);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x01);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x1E);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x1E);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x37);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x37);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x46);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x46);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x44);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4A);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x4A);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x48);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x48);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2C, 0x01);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2D, 0x01);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2E, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2F, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1E);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1E);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x37);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x37);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x0A);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x0A);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0x04);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0x04);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x06);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x02);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x02);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1E);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1E);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4A, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4C, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4D, 0x37);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4E, 0x37);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4F, 0x09);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x09);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0B);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x0B);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x05);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x05);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x07);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x07);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x30);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x16);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x34);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x05);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6A);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x1D);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x6A);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xFF);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xDD);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3F);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x14);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x82);
|
2024-07-04 12:50:17 +08:00
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x04);
|
2024-06-24 22:19:24 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x48);
|
2024-07-04 12:50:17 +08:00
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x00);
|
2024-06-24 22:19:24 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE6, 0x02);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE7, 0x0C);
|
|
|
|
|
drm/panel: jd9365da: Move "exit sleep mode" and "set display on" cmds
Move the "exit sleep mode" and "set display on" command from
enable() to init() function.
As mentioned in the patch:
https://lore.kernel.org/all/20240624141926.5250-2-lvzhaoxiong@huaqin.corp-partner.google.com/
The Mediatek Soc DSI host has different modes in prepare() and
enable() functions, prepare() is in LP mode and enable() is in
HS mode. Since the "exit sleep mode" and "set display on"
command must also be sent in LP mode, so we also move "exit
sleep mode" and "set display on" command to the init() function.
We have no other actions in the enable() function after moves
"exit sleep mode" and "set display on", and we checked the call
of the enable() function during the "startup" process. It seems
that only one judgment was made in drm_panel_enabel(). If the
panel does not define enable(), the judgment will skip the
enable() and continue execution. This does not seem to have
any other effect, and we found that some drivers also seem
to have no enable() function added, for example:
panel-asus-z00t-tm5p5-n35596 / panel-boe-himax8279d...
In addition, we briefly tested the kingdisplay_kd101ne3 panel and
melfas_lmfbx101117480 panel, and it seems that there is no garbage
on the panel, so we delete enable() function.
After moving the "exit sleep mode" and "set display on" command
to the init() function, we no longer need additional delay
judgment, so we delete variables "exit_sleep_to_display_on_delay_ms"
and "display_on_delay_ms".
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com>
Acked-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Link: https://lore.kernel.org/r/20240807100429.13260-2-lvzhaoxiong@huaqin.corp-partner.google.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240807100429.13260-2-lvzhaoxiong@huaqin.corp-partner.google.com
2024-08-07 18:04:28 +08:00
|
|
|
mipi_dsi_msleep(&dsi_ctx, 120);
|
|
|
|
|
|
|
|
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
|
|
|
|
|
|
|
|
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
|
|
|
|
|
2024-06-24 22:19:24 +08:00
|
|
|
return dsi_ctx.accum_err;
|
2022-11-08 23:01:20 +05:30
|
|
|
};
|
|
|
|
|
|
|
|
static const struct jadard_panel_desc cz101b4001_desc = {
|
|
|
|
.mode = {
|
|
|
|
.clock = 70000,
|
|
|
|
|
|
|
|
.hdisplay = 800,
|
|
|
|
.hsync_start = 800 + 40,
|
|
|
|
.hsync_end = 800 + 40 + 18,
|
|
|
|
.htotal = 800 + 40 + 18 + 20,
|
|
|
|
|
|
|
|
.vdisplay = 1280,
|
|
|
|
.vsync_start = 1280 + 20,
|
|
|
|
.vsync_end = 1280 + 20 + 4,
|
|
|
|
.vtotal = 1280 + 20 + 4 + 20,
|
|
|
|
|
|
|
|
.width_mm = 62,
|
|
|
|
.height_mm = 110,
|
|
|
|
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
|
|
|
|
},
|
|
|
|
.lanes = 4,
|
|
|
|
.format = MIPI_DSI_FMT_RGB888,
|
2024-06-24 22:19:24 +08:00
|
|
|
.init = cz101b4001_init_cmds,
|
2022-11-08 23:01:20 +05:30
|
|
|
};
|
|
|
|
|
2024-06-24 22:19:25 +08:00
|
|
|
static int kingdisplay_kd101ne3_init_cmds(struct jadard *jadard)
|
|
|
|
{
|
|
|
|
struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
|
|
|
|
|
2024-07-04 12:50:17 +08:00
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x00);
|
|
|
|
jadard_enable_standard_cmds(&dsi_ctx);
|
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x01);
|
2024-06-24 22:19:25 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xc7);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xc7);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x28);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x12);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x7e);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x6a);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2e);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x61);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x50);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x43);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x3f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x32);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x35);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x38);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x36);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x36);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x54);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x42);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x48);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x39);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x34);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x26);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x14);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x61);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x50);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x43);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x3f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x32);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x35);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x38);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x36);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x36);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x54);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x42);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x48);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x39);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x34);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x26);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x14);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x02);
|
2024-07-04 12:50:17 +08:00
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x02);
|
2024-06-24 22:19:25 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x52);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x50);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x77);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x57);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4e);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x4a);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x48);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x46);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x44);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x40);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x53);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x77);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x57);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4d);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x4b);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x49);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x47);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x45);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x41);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x13);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x01);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x0d);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x0f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x05);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x07);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x09);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0b);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x11);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x12);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x0c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x0e);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x04);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x06);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x0a);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x10);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x6c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x75);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0xb4);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x6c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x0c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xbb);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x05);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a);
|
2024-07-04 12:50:17 +08:00
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x04);
|
2024-06-24 22:19:25 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48);
|
2024-07-04 12:50:17 +08:00
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x00);
|
2024-06-24 22:19:25 +08:00
|
|
|
|
drm/panel: jd9365da: Move "exit sleep mode" and "set display on" cmds
Move the "exit sleep mode" and "set display on" command from
enable() to init() function.
As mentioned in the patch:
https://lore.kernel.org/all/20240624141926.5250-2-lvzhaoxiong@huaqin.corp-partner.google.com/
The Mediatek Soc DSI host has different modes in prepare() and
enable() functions, prepare() is in LP mode and enable() is in
HS mode. Since the "exit sleep mode" and "set display on"
command must also be sent in LP mode, so we also move "exit
sleep mode" and "set display on" command to the init() function.
We have no other actions in the enable() function after moves
"exit sleep mode" and "set display on", and we checked the call
of the enable() function during the "startup" process. It seems
that only one judgment was made in drm_panel_enabel(). If the
panel does not define enable(), the judgment will skip the
enable() and continue execution. This does not seem to have
any other effect, and we found that some drivers also seem
to have no enable() function added, for example:
panel-asus-z00t-tm5p5-n35596 / panel-boe-himax8279d...
In addition, we briefly tested the kingdisplay_kd101ne3 panel and
melfas_lmfbx101117480 panel, and it seems that there is no garbage
on the panel, so we delete enable() function.
After moving the "exit sleep mode" and "set display on" command
to the init() function, we no longer need additional delay
judgment, so we delete variables "exit_sleep_to_display_on_delay_ms"
and "display_on_delay_ms".
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com>
Acked-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Link: https://lore.kernel.org/r/20240807100429.13260-2-lvzhaoxiong@huaqin.corp-partner.google.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240807100429.13260-2-lvzhaoxiong@huaqin.corp-partner.google.com
2024-08-07 18:04:28 +08:00
|
|
|
mipi_dsi_msleep(&dsi_ctx, 120);
|
|
|
|
|
|
|
|
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
|
|
|
|
|
|
|
|
mipi_dsi_msleep(&dsi_ctx, 120);
|
|
|
|
|
|
|
|
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
|
|
|
|
|
|
|
|
mipi_dsi_msleep(&dsi_ctx, 20);
|
|
|
|
|
2024-06-24 22:19:25 +08:00
|
|
|
return dsi_ctx.accum_err;
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct jadard_panel_desc kingdisplay_kd101ne3_40ti_desc = {
|
|
|
|
.mode = {
|
|
|
|
.clock = (800 + 24 + 24 + 24) * (1280 + 30 + 4 + 8) * 60 / 1000,
|
|
|
|
|
|
|
|
.hdisplay = 800,
|
|
|
|
.hsync_start = 800 + 24,
|
|
|
|
.hsync_end = 800 + 24 + 24,
|
|
|
|
.htotal = 800 + 24 + 24 + 24,
|
|
|
|
|
|
|
|
.vdisplay = 1280,
|
|
|
|
.vsync_start = 1280 + 30,
|
|
|
|
.vsync_end = 1280 + 30 + 4,
|
|
|
|
.vtotal = 1280 + 30 + 4 + 8,
|
|
|
|
|
|
|
|
.width_mm = 135,
|
|
|
|
.height_mm = 216,
|
|
|
|
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
|
|
|
|
},
|
|
|
|
.lanes = 4,
|
|
|
|
.format = MIPI_DSI_FMT_RGB888,
|
|
|
|
.init = kingdisplay_kd101ne3_init_cmds,
|
|
|
|
.lp11_before_reset = true,
|
|
|
|
.reset_before_power_off_vcioo = true,
|
|
|
|
.vcioo_to_lp11_delay_ms = 5,
|
|
|
|
.lp11_to_reset_delay_ms = 10,
|
|
|
|
.backlight_off_to_display_off_delay_ms = 100,
|
|
|
|
.display_off_to_enter_sleep_delay_ms = 50,
|
|
|
|
.enter_sleep_to_reset_down_delay_ms = 100,
|
|
|
|
};
|
|
|
|
|
2024-07-04 12:50:16 +08:00
|
|
|
static int melfas_lmfbx101117480_init_cmds(struct jadard *jadard)
|
|
|
|
{
|
|
|
|
struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
|
|
|
|
|
2024-07-04 12:50:17 +08:00
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x00);
|
|
|
|
jadard_enable_standard_cmds(&dsi_ctx);
|
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x01);
|
2024-07-04 12:50:16 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
|
2024-08-07 18:04:29 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xd7);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01);
|
2024-07-04 12:50:16 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);
|
2024-08-07 18:04:29 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xd7);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01);
|
2024-07-04 12:50:16 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x70);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x2d);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x2d);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x7e);
|
2024-08-07 18:04:29 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfd);
|
2024-07-04 12:50:16 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x28);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x12);
|
2024-08-07 18:04:29 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x7e);
|
2024-07-04 12:50:16 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01);
|
2024-08-07 18:04:29 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x6a);
|
2024-07-04 12:50:16 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x09);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2e);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x15);
|
2024-08-07 18:04:29 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x73);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x56);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x43);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x38);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x36);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x28);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x19);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x32);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x31);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x31);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x4f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x3e);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x47);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x36);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x31);
|
2024-07-04 12:50:16 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x24);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x12);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02);
|
2024-08-07 18:04:29 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x73);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x56);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x43);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x38);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x36);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x28);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x19);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x32);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x31);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x31);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x4f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x3e);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x47);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x36);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x31);
|
2024-07-04 12:50:16 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x24);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x12);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x02);
|
2024-07-04 12:50:17 +08:00
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x02);
|
2024-07-04 12:50:16 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x52);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x50);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x77);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x57);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4e);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x4a);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x48);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x46);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x44);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x40);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x53);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x77);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x57);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4d);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x5f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x4b);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x49);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x47);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x45);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x41);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x55);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x13);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x01);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x37);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x0d);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x0f);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x05);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x07);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x09);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0b);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x11);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x12);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x37);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x0c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x0e);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x04);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x06);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x0a);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x10);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x15);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x6c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x75);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0xb4);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x6c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x0c);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xbb);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x05);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a);
|
2024-07-04 12:50:17 +08:00
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x04);
|
2024-07-04 12:50:16 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x23);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x11);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x49);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x08);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x03);
|
2024-07-04 12:50:17 +08:00
|
|
|
|
|
|
|
jd9365da_switch_page(&dsi_ctx, 0x00);
|
2024-07-04 12:50:16 +08:00
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x02);
|
|
|
|
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe7, 0x06);
|
|
|
|
|
drm/panel: jd9365da: Move "exit sleep mode" and "set display on" cmds
Move the "exit sleep mode" and "set display on" command from
enable() to init() function.
As mentioned in the patch:
https://lore.kernel.org/all/20240624141926.5250-2-lvzhaoxiong@huaqin.corp-partner.google.com/
The Mediatek Soc DSI host has different modes in prepare() and
enable() functions, prepare() is in LP mode and enable() is in
HS mode. Since the "exit sleep mode" and "set display on"
command must also be sent in LP mode, so we also move "exit
sleep mode" and "set display on" command to the init() function.
We have no other actions in the enable() function after moves
"exit sleep mode" and "set display on", and we checked the call
of the enable() function during the "startup" process. It seems
that only one judgment was made in drm_panel_enabel(). If the
panel does not define enable(), the judgment will skip the
enable() and continue execution. This does not seem to have
any other effect, and we found that some drivers also seem
to have no enable() function added, for example:
panel-asus-z00t-tm5p5-n35596 / panel-boe-himax8279d...
In addition, we briefly tested the kingdisplay_kd101ne3 panel and
melfas_lmfbx101117480 panel, and it seems that there is no garbage
on the panel, so we delete enable() function.
After moving the "exit sleep mode" and "set display on" command
to the init() function, we no longer need additional delay
judgment, so we delete variables "exit_sleep_to_display_on_delay_ms"
and "display_on_delay_ms".
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com>
Acked-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Link: https://lore.kernel.org/r/20240807100429.13260-2-lvzhaoxiong@huaqin.corp-partner.google.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240807100429.13260-2-lvzhaoxiong@huaqin.corp-partner.google.com
2024-08-07 18:04:28 +08:00
|
|
|
mipi_dsi_msleep(&dsi_ctx, 120);
|
|
|
|
|
|
|
|
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
|
|
|
|
|
|
|
|
mipi_dsi_msleep(&dsi_ctx, 120);
|
|
|
|
|
|
|
|
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
|
|
|
|
|
|
|
|
mipi_dsi_msleep(&dsi_ctx, 20);
|
|
|
|
|
2024-07-04 12:50:16 +08:00
|
|
|
return dsi_ctx.accum_err;
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct jadard_panel_desc melfas_lmfbx101117480_desc = {
|
|
|
|
.mode = {
|
|
|
|
.clock = (800 + 24 + 24 + 24) * (1280 + 30 + 4 + 8) * 60 / 1000,
|
|
|
|
|
|
|
|
.hdisplay = 800,
|
|
|
|
.hsync_start = 800 + 24,
|
|
|
|
.hsync_end = 800 + 24 + 24,
|
|
|
|
.htotal = 800 + 24 + 24 + 24,
|
|
|
|
|
|
|
|
.vdisplay = 1280,
|
|
|
|
.vsync_start = 1280 + 30,
|
|
|
|
.vsync_end = 1280 + 30 + 4,
|
|
|
|
.vtotal = 1280 + 30 + 4 + 8,
|
|
|
|
|
|
|
|
.width_mm = 135,
|
|
|
|
.height_mm = 216,
|
|
|
|
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
|
|
|
|
},
|
|
|
|
.lanes = 4,
|
|
|
|
.format = MIPI_DSI_FMT_RGB888,
|
|
|
|
.init = melfas_lmfbx101117480_init_cmds,
|
|
|
|
.lp11_before_reset = true,
|
|
|
|
.reset_before_power_off_vcioo = true,
|
|
|
|
.vcioo_to_lp11_delay_ms = 5,
|
|
|
|
.lp11_to_reset_delay_ms = 10,
|
|
|
|
.backlight_off_to_display_off_delay_ms = 100,
|
|
|
|
.display_off_to_enter_sleep_delay_ms = 50,
|
|
|
|
.enter_sleep_to_reset_down_delay_ms = 100,
|
|
|
|
};
|
|
|
|
|
2022-11-08 23:01:20 +05:30
|
|
|
static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
|
|
|
|
{
|
|
|
|
struct device *dev = &dsi->dev;
|
|
|
|
const struct jadard_panel_desc *desc;
|
|
|
|
struct jadard *jadard;
|
|
|
|
int ret;
|
|
|
|
|
2025-05-20 22:03:44 -05:00
|
|
|
jadard = devm_drm_panel_alloc(dev, struct jadard, panel, &jadard_funcs,
|
|
|
|
DRM_MODE_CONNECTOR_DSI);
|
|
|
|
if (IS_ERR(jadard))
|
|
|
|
return PTR_ERR(jadard);
|
2022-11-08 23:01:20 +05:30
|
|
|
|
|
|
|
desc = of_device_get_match_data(dev);
|
|
|
|
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
|
|
|
|
MIPI_DSI_MODE_NO_EOT_PACKET;
|
|
|
|
dsi->format = desc->format;
|
|
|
|
dsi->lanes = desc->lanes;
|
|
|
|
|
2024-09-27 09:53:05 -04:00
|
|
|
jadard->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
|
2022-11-08 23:01:20 +05:30
|
|
|
if (IS_ERR(jadard->reset)) {
|
|
|
|
DRM_DEV_ERROR(&dsi->dev, "failed to get our reset GPIO\n");
|
|
|
|
return PTR_ERR(jadard->reset);
|
|
|
|
}
|
|
|
|
|
|
|
|
jadard->vdd = devm_regulator_get(dev, "vdd");
|
|
|
|
if (IS_ERR(jadard->vdd)) {
|
|
|
|
DRM_DEV_ERROR(&dsi->dev, "failed to get vdd regulator\n");
|
|
|
|
return PTR_ERR(jadard->vdd);
|
|
|
|
}
|
|
|
|
|
|
|
|
jadard->vccio = devm_regulator_get(dev, "vccio");
|
|
|
|
if (IS_ERR(jadard->vccio)) {
|
|
|
|
DRM_DEV_ERROR(&dsi->dev, "failed to get vccio regulator\n");
|
|
|
|
return PTR_ERR(jadard->vccio);
|
|
|
|
}
|
|
|
|
|
2024-06-24 22:19:26 +08:00
|
|
|
ret = of_drm_get_panel_orientation(dev->of_node, &jadard->orientation);
|
|
|
|
if (ret < 0)
|
|
|
|
return dev_err_probe(dev, ret, "failed to get orientation\n");
|
|
|
|
|
2022-11-08 23:01:20 +05:30
|
|
|
ret = drm_panel_of_backlight(&jadard->panel);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
drm_panel_add(&jadard->panel);
|
|
|
|
|
|
|
|
mipi_dsi_set_drvdata(dsi, jadard);
|
|
|
|
jadard->dsi = dsi;
|
|
|
|
jadard->desc = desc;
|
|
|
|
|
|
|
|
ret = mipi_dsi_attach(dsi);
|
|
|
|
if (ret < 0)
|
|
|
|
drm_panel_remove(&jadard->panel);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void jadard_dsi_remove(struct mipi_dsi_device *dsi)
|
|
|
|
{
|
|
|
|
struct jadard *jadard = mipi_dsi_get_drvdata(dsi);
|
|
|
|
|
|
|
|
mipi_dsi_detach(dsi);
|
|
|
|
drm_panel_remove(&jadard->panel);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id jadard_of_match[] = {
|
2023-01-24 00:03:10 +05:30
|
|
|
{
|
|
|
|
.compatible = "chongzhou,cz101b4001",
|
|
|
|
.data = &cz101b4001_desc
|
|
|
|
},
|
2024-06-24 22:19:25 +08:00
|
|
|
{
|
|
|
|
.compatible = "kingdisplay,kd101ne3-40ti",
|
|
|
|
.data = &kingdisplay_kd101ne3_40ti_desc
|
|
|
|
},
|
2024-07-04 12:50:16 +08:00
|
|
|
{
|
|
|
|
.compatible = "melfas,lmfbx101117480",
|
|
|
|
.data = &melfas_lmfbx101117480_desc
|
|
|
|
},
|
2023-01-24 00:03:10 +05:30
|
|
|
{
|
|
|
|
.compatible = "radxa,display-10hd-ad001",
|
|
|
|
.data = &cz101b4001_desc
|
|
|
|
},
|
2023-01-24 00:03:12 +05:30
|
|
|
{
|
|
|
|
.compatible = "radxa,display-8hd-ad002",
|
|
|
|
.data = &radxa_display_8hd_ad002_desc
|
|
|
|
},
|
2022-11-08 23:01:20 +05:30
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, jadard_of_match);
|
|
|
|
|
|
|
|
static struct mipi_dsi_driver jadard_driver = {
|
|
|
|
.probe = jadard_dsi_probe,
|
|
|
|
.remove = jadard_dsi_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "jadard-jd9365da",
|
|
|
|
.of_match_table = jadard_of_match,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
module_mipi_dsi_driver(jadard_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Jagan Teki <jagan@edgeble.ai>");
|
|
|
|
MODULE_AUTHOR("Stephen Chen <stephen@radxa.com>");
|
|
|
|
MODULE_DESCRIPTION("Jadard JD9365DA-H3 WXGA DSI panel");
|
|
|
|
MODULE_LICENSE("GPL");
|