linux/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/Five SMARC EVK carrier board
 *
 * Copyright (C) 2022 Renesas Electronics Corp.
 */

#include <arm64/renesas/rzg2ul-smarc.dtsi>
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Enable the minimal blocks required for booting the Renesas RZ/Five SMARC EVK with initramfs. Below are the blocks which are enabled: - CPG - CPU0 - DDR (memory regions) - PINCTRL - PLIC - SCIF0 As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and carrier [2] board DTSIs which enables almost all the blocks supported by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually enabling the blocks hence the aliases for ETH/I2C are deleted and rest of the IP blocks are marked as disabled/deleted. [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi [2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20221028165921.94487-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2022-10-28 17:59:19 +01:00			`// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)`
			`/*`
			`* Device Tree Source for the RZ/Five SMARC EVK carrier board`
			`*`
			`* Copyright (C) 2022 Renesas Electronics Corp.`
			`*/`

			`#include <arm64/renesas/rzg2ul-smarc.dtsi>`