Martin Tsai ffb6c1c6c5 drm/amd/display: Redefine DMCU_SCRATCH to identify DMCU state ... [why] To resume system before entering S0i3 completely will cause PSP not reload DMCU FW since there is not HW power state change. In this case, driver cannot get correct DMCU version from IRAM since driver override it and DMCU didn't reload to update it. It makes driver return false in dcn10_dmcu_init(). [how] 1.To redefine DMCU_SCRATCH to identify different DMCU state. 2.To reserve IRAM 0xF0~0xFF write by DMCU only. 3.To remove dcn10_get_dmcu_state Signed-off-by: Martin Tsai <martin.tsai@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-01-14 15:39:22 -05:00
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hw	drm/amd/display: Redefine DMCU_SCRATCH to identify DMCU state	2019-01-14 15:39:22 -05:00
bw_fixed.h	drm/amd/display: explicit uint64_t casting	2018-11-05 14:20:50 -05:00
clock_source.h	drm/amd/display: Use 100 Hz precision for pipe pixel clocks	2019-01-14 15:04:39 -05:00
compressor.h	drm/amd/display: fbc state could not reach while enable fbc	2018-11-30 12:02:35 -05:00
core_status.h	drm/amd/display: Improve logging of validation failures during atomic_check	2019-01-14 15:04:40 -05:00
core_types.h	drm/amd/display: add dsclk to pipe bw struct	2019-01-14 15:04:42 -05:00
custom_float.h
dc_link_ddc.h	drm/amd/display: Return aux replies directly to DRM	2018-07-13 14:48:36 -05:00
dc_link_dp.h	drm/amd/display: Retry link training again	2018-07-27 09:07:42 -05:00
dce_calcs.h	drm/amdgpu/display: remove VEGAM config option	2018-05-18 16:08:18 -05:00
dcn_calcs.h	drm/amd/display: rename dccg to clk_mgr	2018-11-05 14:20:48 -05:00
hw_sequencer.h	drm/amd/display: make underflow status clear explicit	2018-11-19 15:27:36 -05:00
link_hwss.h
reg_helper.h	drm/amd/display: generic indirect register access	2018-07-13 14:47:33 -05:00
resource.h	drm/amd/display: move pplib/smu notification to dccg block	2018-11-05 14:20:40 -05:00