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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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ffaf1de2f6
This patch add support for the writing and reading of the phy registers. LAN937x uses the Vphy indirect addressing method for accessing the phys. Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
270 lines
6.6 KiB
C
270 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Microchip LAN937X switch driver main logic
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* Copyright (C) 2019-2022 Microchip Technology Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/iopoll.h>
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#include <linux/phy.h>
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#include <linux/of_net.h>
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#include <linux/if_bridge.h>
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#include <linux/math.h>
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#include <net/dsa.h>
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#include <net/switchdev.h>
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#include "lan937x_reg.h"
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#include "ksz_common.h"
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#include "lan937x.h"
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static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
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{
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return regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
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}
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static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset,
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u8 bits, bool set)
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{
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return regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
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bits, set ? bits : 0);
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}
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static int lan937x_enable_spi_indirect_access(struct ksz_device *dev)
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{
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u16 data16;
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int ret;
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/* Enable Phy access through SPI */
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ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false);
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if (ret < 0)
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return ret;
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ret = ksz_read16(dev, REG_VPHY_SPECIAL_CTRL__2, &data16);
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if (ret < 0)
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return ret;
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/* Allow SPI access */
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data16 |= VPHY_SPI_INDIRECT_ENABLE;
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return ksz_write16(dev, REG_VPHY_SPECIAL_CTRL__2, data16);
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}
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static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg)
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{
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u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE;
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u16 temp;
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/* get register address based on the logical port */
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temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2)));
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return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp);
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}
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static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg,
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u16 val)
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{
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unsigned int value;
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int ret;
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/* Check for internal phy port */
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if (!dev->info->internal_phy[addr])
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return -EOPNOTSUPP;
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ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
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if (ret < 0)
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return ret;
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/* Write the data to be written to the VPHY reg */
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ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val);
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if (ret < 0)
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return ret;
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/* Write the Write En and Busy bit */
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ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2,
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(VPHY_IND_WRITE | VPHY_IND_BUSY));
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if (ret < 0)
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return ret;
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ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2,
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value, !(value & VPHY_IND_BUSY), 10,
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1000);
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if (ret < 0) {
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dev_err(dev->dev, "Failed to write phy register\n");
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return ret;
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}
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return 0;
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}
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static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg,
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u16 *val)
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{
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unsigned int value;
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int ret;
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/* Check for internal phy port, return 0xffff for non-existent phy */
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if (!dev->info->internal_phy[addr])
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return 0xffff;
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ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
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if (ret < 0)
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return ret;
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/* Write Read and Busy bit to start the transaction */
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ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY);
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if (ret < 0)
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return ret;
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ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2,
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value, !(value & VPHY_IND_BUSY), 10,
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1000);
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if (ret < 0) {
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dev_err(dev->dev, "Failed to read phy register\n");
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return ret;
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}
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/* Read the VPHY register which has the PHY data */
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return ksz_read16(dev, REG_VPHY_IND_DATA__2, val);
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}
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void lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data)
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{
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lan937x_internal_phy_read(dev, addr, reg, data);
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}
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void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val)
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{
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lan937x_internal_phy_write(dev, addr, reg, val);
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}
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int lan937x_reset_switch(struct ksz_device *dev)
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{
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u32 data32;
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int ret;
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/* reset switch */
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ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
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if (ret < 0)
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return ret;
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/* Enable Auto Aging */
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ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true);
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if (ret < 0)
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return ret;
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/* disable interrupts */
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ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
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if (ret < 0)
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return ret;
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ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF);
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if (ret < 0)
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return ret;
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return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
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}
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void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port)
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{
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struct dsa_switch *ds = dev->ds;
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u8 member;
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/* enable tag tail for host port */
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if (cpu_port)
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lan937x_port_cfg(dev, port, REG_PORT_CTRL_0,
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PORT_TAIL_TAG_ENABLE, true);
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/* disable frame check length field */
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lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, PORT_CHECK_LENGTH,
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false);
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/* set back pressure for half duplex */
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lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE,
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true);
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/* enable 802.1p priority */
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lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
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if (!dev->info->internal_phy[port])
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lan937x_port_cfg(dev, port, REG_PORT_XMII_CTRL_0,
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PORT_MII_TX_FLOW_CTRL | PORT_MII_RX_FLOW_CTRL,
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true);
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if (cpu_port)
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member = dsa_user_ports(ds);
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else
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member = BIT(dsa_upstream_port(ds, port));
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dev->dev_ops->cfg_port_member(dev, port, member);
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}
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void lan937x_config_cpu_port(struct dsa_switch *ds)
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{
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struct ksz_device *dev = ds->priv;
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struct dsa_port *dp;
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dsa_switch_for_each_cpu_port(dp, ds) {
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if (dev->info->cpu_ports & (1 << dp->index)) {
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dev->cpu_port = dp->index;
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/* enable cpu port */
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lan937x_port_setup(dev, dp->index, true);
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}
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}
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dsa_switch_for_each_user_port(dp, ds) {
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ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED);
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}
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}
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int lan937x_setup(struct dsa_switch *ds)
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{
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struct ksz_device *dev = ds->priv;
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int ret;
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/* enable Indirect Access from SPI to the VPHY registers */
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ret = lan937x_enable_spi_indirect_access(dev);
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if (ret < 0) {
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dev_err(dev->dev, "failed to enable spi indirect access");
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return ret;
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}
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/* The VLAN aware is a global setting. Mixed vlan
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* filterings are not supported.
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*/
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ds->vlan_filtering_is_global = true;
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/* Enable aggressive back off for half duplex & UNH mode */
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lan937x_cfg(dev, REG_SW_MAC_CTRL_0,
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(SW_PAUSE_UNH_MODE | SW_NEW_BACKOFF | SW_AGGR_BACKOFF),
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true);
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/* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop
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* packets when 16 or more collisions occur
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*/
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lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true);
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/* enable global MIB counter freeze function */
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lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
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/* disable CLK125 & CLK25, 1: disable, 0: enable */
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lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
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(SW_CLK125_ENB | SW_CLK25_ENB), true);
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return 0;
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}
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int lan937x_switch_init(struct ksz_device *dev)
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{
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dev->port_mask = (1 << dev->info->port_cnt) - 1;
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return 0;
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}
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void lan937x_switch_exit(struct ksz_device *dev)
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{
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lan937x_reset_switch(dev);
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}
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MODULE_AUTHOR("Arun Ramadoss <arun.ramadoss@microchip.com>");
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MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver");
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MODULE_LICENSE("GPL");
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