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ff20783f7b
Clocks that don't have a pre-divider don't list any pre-divider
in their frequency tables, but their tables are initialized using
aggregate initializers. Use tagged initializers so we properly
assign the m and n values for each frequency. Furthermore, the
mmcc_pxo_pll8_pll2_pll3 array improperly mapped the second
element to pll2 instead of pll8, causing the clock driver to
recalculate the wrong rate for any clocks using this array along
with a rate that uses pll2. Plus the .num_parents field is 3
instead of 4 so you can't even switch the parent to pll3. Finally
I noticed that the jpegd clock improperly indicates that the
pre-divider width is only 2, when it's actually 4 bits wide.
Fixes:
|
||
|---|---|---|
| .. | ||
| clk-branch.c | ||
| clk-branch.h | ||
| clk-pll.c | ||
| clk-pll.h | ||
| clk-rcg.c | ||
| clk-rcg.h | ||
| clk-rcg2.c | ||
| clk-regmap.c | ||
| clk-regmap.h | ||
| common.c | ||
| common.h | ||
| gcc-apq8084.c | ||
| gcc-ipq806x.c | ||
| gcc-msm8660.c | ||
| gcc-msm8960.c | ||
| gcc-msm8974.c | ||
| Kconfig | ||
| Makefile | ||
| mmcc-apq8084.c | ||
| mmcc-msm8960.c | ||
| mmcc-msm8974.c | ||
| reset.c | ||
| reset.h | ||