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			irq_domain_add_*() interfaces are going away as being obsolete now. Switch to the preferred irq_domain_create_*() ones. Those differ in the node parameter: They take more generic struct fwnode_handle instead of struct device_node. Therefore, of_fwnode_handle() is added around the original parameter. Note some of the users can likely use dev->fwnode directly instead of indirect of_fwnode_handle(dev->of_node). But dev->fwnode is not guaranteed to be set for all, so this has to be investigated on case to case basis (by people who can actually test with the HW). [ tglx: Fix up subject prefix ] Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/all/20250319092951.37667-22-jirislaby@kernel.org
		
			
				
	
	
		
			174 lines
		
	
	
	
		
			4.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			174 lines
		
	
	
	
		
			4.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0-only
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| /*
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|  * Copyright (C) 2020 Birger Koblitz <mail@birger-koblitz.de>
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|  * Copyright (C) 2020 Bert Vermeulen <bert@biot.com>
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|  * Copyright (C) 2020 John Crispin <john@phrozen.org>
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|  */
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| 
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| #include <linux/of_irq.h>
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| #include <linux/irqchip.h>
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| #include <linux/spinlock.h>
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| #include <linux/of_address.h>
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| #include <linux/irqchip/chained_irq.h>
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| 
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| /* Global Interrupt Mask Register */
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| #define RTL_ICTL_GIMR		0x00
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| /* Global Interrupt Status Register */
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| #define RTL_ICTL_GISR		0x04
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| /* Interrupt Routing Registers */
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| #define RTL_ICTL_IRR0		0x08
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| #define RTL_ICTL_IRR1		0x0c
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| #define RTL_ICTL_IRR2		0x10
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| #define RTL_ICTL_IRR3		0x14
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| 
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| #define RTL_ICTL_NUM_INPUTS	32
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| 
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| #define REG(x)		(realtek_ictl_base + x)
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| 
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| static DEFINE_RAW_SPINLOCK(irq_lock);
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| static void __iomem *realtek_ictl_base;
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| 
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| /*
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|  * IRR0-IRR3 store 4 bits per interrupt, but Realtek uses inverted numbering,
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|  * placing IRQ 31 in the first four bits. A routing value of '0' means the
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|  * interrupt is left disconnected. Routing values {1..15} connect to output
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|  * lines {0..14}.
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|  */
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| #define IRR_OFFSET(idx)		(4 * (3 - (idx * 4) / 32))
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| #define IRR_SHIFT(idx)		((idx * 4) % 32)
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| 
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| static void write_irr(void __iomem *irr0, int idx, u32 value)
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| {
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| 	unsigned int offset = IRR_OFFSET(idx);
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| 	unsigned int shift = IRR_SHIFT(idx);
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| 	u32 irr;
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| 
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| 	irr = readl(irr0 + offset) & ~(0xf << shift);
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| 	irr |= (value & 0xf) << shift;
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| 	writel(irr, irr0 + offset);
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| }
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| 
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| static void realtek_ictl_unmask_irq(struct irq_data *i)
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| {
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| 	unsigned long flags;
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| 	u32 value;
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| 
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| 	raw_spin_lock_irqsave(&irq_lock, flags);
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| 
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| 	value = readl(REG(RTL_ICTL_GIMR));
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| 	value |= BIT(i->hwirq);
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| 	writel(value, REG(RTL_ICTL_GIMR));
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| 
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| 	raw_spin_unlock_irqrestore(&irq_lock, flags);
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| }
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| 
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| static void realtek_ictl_mask_irq(struct irq_data *i)
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| {
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| 	unsigned long flags;
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| 	u32 value;
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| 
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| 	raw_spin_lock_irqsave(&irq_lock, flags);
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| 
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| 	value = readl(REG(RTL_ICTL_GIMR));
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| 	value &= ~BIT(i->hwirq);
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| 	writel(value, REG(RTL_ICTL_GIMR));
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| 
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| 	raw_spin_unlock_irqrestore(&irq_lock, flags);
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| }
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| 
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| static struct irq_chip realtek_ictl_irq = {
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| 	.name = "realtek-rtl-intc",
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| 	.irq_mask = realtek_ictl_mask_irq,
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| 	.irq_unmask = realtek_ictl_unmask_irq,
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| };
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| 
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| static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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| {
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| 	unsigned long flags;
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| 
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| 	irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq);
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| 
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| 	raw_spin_lock_irqsave(&irq_lock, flags);
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| 	write_irr(REG(RTL_ICTL_IRR0), hw, 1);
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| 	raw_spin_unlock_irqrestore(&irq_lock, flags);
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| 
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| 	return 0;
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| }
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| 
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| static const struct irq_domain_ops irq_domain_ops = {
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| 	.map = intc_map,
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| 	.xlate = irq_domain_xlate_onecell,
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| };
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| 
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| static void realtek_irq_dispatch(struct irq_desc *desc)
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| {
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| 	struct irq_chip *chip = irq_desc_get_chip(desc);
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| 	struct irq_domain *domain;
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| 	unsigned long pending;
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| 	unsigned int soc_int;
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| 
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| 	chained_irq_enter(chip, desc);
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| 	pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR));
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| 
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| 	if (unlikely(!pending)) {
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| 		spurious_interrupt();
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| 		goto out;
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| 	}
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| 
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| 	domain = irq_desc_get_handler_data(desc);
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| 	for_each_set_bit(soc_int, &pending, 32)
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| 		generic_handle_domain_irq(domain, soc_int);
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| 
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| out:
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| 	chained_irq_exit(chip, desc);
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| }
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| 
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| static int __init realtek_rtl_of_init(struct device_node *node, struct device_node *parent)
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| {
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| 	struct of_phandle_args oirq;
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| 	struct irq_domain *domain;
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| 	unsigned int soc_irq;
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| 	int parent_irq;
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| 
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| 	realtek_ictl_base = of_iomap(node, 0);
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| 	if (!realtek_ictl_base)
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| 		return -ENXIO;
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| 
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| 	/* Disable all cascaded interrupts and clear routing */
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| 	writel(0, REG(RTL_ICTL_GIMR));
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| 	for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++)
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| 		write_irr(REG(RTL_ICTL_IRR0), soc_irq, 0);
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| 
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| 	if (WARN_ON(!of_irq_count(node))) {
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| 		/*
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| 		 * If DT contains no parent interrupts, assume MIPS CPU IRQ 2
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| 		 * (HW0) is connected to the first output. This is the case for
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| 		 * all known hardware anyway. "interrupt-map" is deprecated, so
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| 		 * don't bother trying to parse that.
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| 		 */
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| 		oirq.np = of_find_compatible_node(NULL, NULL, "mti,cpu-interrupt-controller");
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| 		oirq.args_count = 1;
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| 		oirq.args[0] = 2;
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| 
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| 		parent_irq = irq_create_of_mapping(&oirq);
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| 
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| 		of_node_put(oirq.np);
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| 	} else {
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| 		parent_irq = of_irq_get(node, 0);
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| 	}
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| 
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| 	if (parent_irq < 0)
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| 		return parent_irq;
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| 	else if (!parent_irq)
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| 		return -ENODEV;
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| 
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| 	domain = irq_domain_create_linear(of_fwnode_handle(node), RTL_ICTL_NUM_INPUTS, &irq_domain_ops, NULL);
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| 	if (!domain)
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| 		return -ENOMEM;
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| 
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| 	irq_set_chained_handler_and_data(parent_irq, realtek_irq_dispatch, domain);
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| 
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| 	return 0;
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| }
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| 
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| IRQCHIP_DECLARE(realtek_rtl_intc, "realtek,rtl-intc", realtek_rtl_of_init);
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