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fc1347b5fe
Platform specific function to assign a register set to a Logical Partition. The "ibm,mmio-atsd" property, provided by the firmware, contains the 16 base ATSD physical addresses (ATSD0 through ATSD15) of the set of MMIO registers (XTS MMIO ATSDx LPARID/AVA/launch/status register). For the time being, the ATSD0 set of registers is used by default. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Acked-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20201125155013.39955-2-clombard@linux.vnet.ibm.com
34 lines
1.4 KiB
C
34 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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// Copyright 2017 IBM Corp.
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#ifndef _ASM_PNV_OCXL_H
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#define _ASM_PNV_OCXL_H
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#include <linux/pci.h>
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#define PNV_OCXL_TL_MAX_TEMPLATE 63
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#define PNV_OCXL_TL_BITS_PER_RATE 4
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#define PNV_OCXL_TL_RATE_BUF_SIZE ((PNV_OCXL_TL_MAX_TEMPLATE+1) * PNV_OCXL_TL_BITS_PER_RATE / 8)
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int pnv_ocxl_get_actag(struct pci_dev *dev, u16 *base, u16 *enabled, u16 *supported);
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int pnv_ocxl_get_pasid_count(struct pci_dev *dev, int *count);
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int pnv_ocxl_get_tl_cap(struct pci_dev *dev, long *cap,
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char *rate_buf, int rate_buf_size);
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int pnv_ocxl_set_tl_conf(struct pci_dev *dev, long cap,
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uint64_t rate_buf_phys, int rate_buf_size);
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int pnv_ocxl_get_xsl_irq(struct pci_dev *dev, int *hwirq);
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void pnv_ocxl_unmap_xsl_regs(void __iomem *dsisr, void __iomem *dar,
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void __iomem *tfc, void __iomem *pe_handle);
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int pnv_ocxl_map_xsl_regs(struct pci_dev *dev, void __iomem **dsisr,
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void __iomem **dar, void __iomem **tfc,
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void __iomem **pe_handle);
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int pnv_ocxl_spa_setup(struct pci_dev *dev, void *spa_mem, int PE_mask, void **platform_data);
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void pnv_ocxl_spa_release(void *platform_data);
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int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle);
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int pnv_ocxl_map_lpar(struct pci_dev *dev, uint64_t lparid,
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uint64_t lpcr, void __iomem **arva);
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void pnv_ocxl_unmap_lpar(void __iomem *arva);
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#endif /* _ASM_PNV_OCXL_H */
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